Questions about the internal SRAM of S32G Hi， I recently tested the bootloader to boot multi-core programs and found that the bootloader will move the complete bin file of each M7 core from QSPI to internal SRAM and then execute it. However, I noticed that the internal SRAM of S32G2 is only 8M, and the space allocated to each M7 core in LD is about 1M. Question: If my M7 core program is very large, such as 10M, how should I operate it? thanks， Re: Questions about the internal SRAM of S32G Hi chenyi, As we know, if multi-core is enabled, it takes a long time for A-core to boot Linux. During the startup of Core A, if Core M collects 100MB of data that requires saving, how should this be handled? I'm having this problem right now.S32G QSPI issue - NXP Community Re: Questions about the internal SRAM of S32G Hello, @youke
Thanks for your reply.
In common, the 8M of SRAM should be bigger enough to run a M7 application, I suggest checking the code to reduce the size.
Regarding to XIP, yes, it is theoretically supported, but there are no example or some documentations about XIP on S32G. It's not easy and not common to implement XIP from NOR flash on S32G, the S32G didn't have internal nor flash, so the cpu can not directly access the nor flash. you could use a bootloader to initialize the QSPI controller and DDR controller at first and then let cpu to execute the application stored in Qflash or DDR on running time.
I hope it will help.
BR
Chenyin
Re: Questions about the internal SRAM of S32G hi, 已解决: S32G2xx M7 execute code from external flash ? - NXP Community I saw this document introducing an XIP(eXecute-In-Place) mechanism that can execute code from external flash. Do you have any relevant materials or demos? thanks Re: Questions about the internal SRAM of S32G Hello, @youke
Thanks for you reply.
As per my understanding, there is not formal sample/document regarding to this topic, you may reference the ddr init code from A53 side if willing to initialize the DDR for M7 side.
Sorry for your inconvenience.
BR
Chenyin Re: Questions about the internal SRAM of S32G hi， Do you have any relevant demos or materials within NXP? thanks Re: Questions about the internal SRAM of S32G Hello, @youke
Thanks for your reply.
Yes, I think both method may work for your situation, but as far as I know , most customers do not use DDR from M core side, it is one option to solve your specific case.
BR
Chenyin Re: Questions about the internal SRAM of S32G Hi， What do you mean, if the M core wants to execute a large image, there are two options: 1. M7 first transfers a portion of the code to the internal SRAM for initializing DDR. After initializing DDR, the complete code is transferred to DDR for execution; 2. The M7 core waits first, and after the A core initializes the DDR, it moves the M7 core image to the DDR and executes it; Is that so? Re: Questions about the internal SRAM of S32G Hello, @youke
Thank for the reply.
If the large size image is indeed caused by code(for example, large libs linked) and cannot be resized via linker file, then it cannot be directly loaded to the SRAM to run. if so, I think you may have to initialize the DDR for running the code.
But, unlike A53 side, the DDR is not by default enabled from sample code/bootloader from M7 side.
BR
Chenyin Re: Questions about the internal SRAM of S32G hi, Thank you for your reply Because I have written too much code, the compiled file is very large. Based on your answer, S32G2 does not support M7 core images exceeding 8MB because they cannot be copied to internal SRAM for execution. Is that correct? Re: Questions about the internal SRAM of S32G Hello, @youke
Thanks for your reply.
I am not sure why your images are so large, since they have been far larger than the 8M ram size(24 M in total).
One possible method is to check the linker file, for example, edit it to make it to 1-2M size each.
Then re-build 3 images, note that do not overlap the address of each other.
If the big size of image is because multi-libs linked(large sized libs), then edit the linker file may not work for the case from my understanding.
BR
Chenyin Re: Questions about the internal SRAM of S32G Hi， We will use three M7 cores to run separate programs here, with each core having an image size of approximately 8M, totaling 24M, Because the internal SRAM of S32G2 is only 8MB, how should I plan the LD file thanks, Re: Questions about the internal SRAM of S32G Hello, @youke Thanks for your post.
In common, the actual size of the M7 image would not be that so big, if so, I suggest modify the linker file to change the address range of each part, thus resize the image.
BR
Chenyin
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