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i.MX95 SEMA42 GATEn regiser of Domain ID

I am planning to use SEMA42 on the i.MX95 to implement mutual exclusion between the Cortex-M7 and the Cortex-A55.
To do this, a domain number (Domain 0–14) needs to be specified in the GTFSM field (bits 3-0) of the SEMA42 GATEn register.
Could you please tell me which bus master (Cortex-A55, Cortex-M7, Cortex-M33, DMA, etc.) each of Domain 0–14 corresponds to?
I was able to find the domain numbers for the Cortex-M7 and Cortex-M33 from the SEMA42 driver example in the MCUXpresso SDK
(APP_CORTEX_M33_DID = 8, APP_CORTEX_M7_DID = 9), and the example works with these values.
However, they do not match the TRDC DIDs configured in the System Manager cfg file (did=2 for the M33/SM and did=4 for the M7).
In addition, the SEMA42 example for the i.MX943 EVK describes these values as a "Master ID assignment for the SoC", so I assume SEMA42 uses the bus master ID rather than the TRDC DID.
However, I could not find the corresponding value for the Cortex-A55 on the i.MX95. If this information (e.g., a master ID assignment table for the i.MX95) is described in any document
or on the web, I would also appreciate it if you could point me to it.

mcuxpresso-sdk\mcuxsdk\examples\_boards\imx95lpd5evk19\driver_examples\sema42\sm\cm7\app.h

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#define APP_CORTEX_M7_DID 9
#define APP_CORTEX_M33_DID 8

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Re: i.MX95 SEMA42 GATEn regiser of Domain ID

Use DID 9 for the Cortex-M7 in the i.MX95 SEMA42 example, not the System Manager/TRDC DID of 4. They are different identifiers in this configuration: SEMA42 accepts the SDK value, and a gate locked by domain 9 reads back GTFSM = 10 (domain + 1).

Re: i.MX95 SEMA42 GATEn regiser of Domain ID

Cortex-M7 DID of the System Manager/TRDC configuration in my environment is 4.

I first tried this DID. But SEMA42 didn't work. GATEn.GTFSM value of MCUXpressoSDK example only work.

Do you have a idea?

Re: i.MX95 SEMA42で使用するDomain ID

The i.MX95 Reference Manual lists Cortex-A55 as Domain ID 3 by default . Its default IDs for Cortex-M7 and Cortex-M33 are 4 and 2, respectively.

Your SDK example instead defines M7 as 9 and M33 as 8. Check the System Manager/TRDC configuration used by that example before using A55 DID 3 for A55–M7 locking. Also, a locked GATEn.GTFSM reads back as DID + 1 ; a readback value of 9 indicates DID 8.

i.MX95リファレンスマニュアルでは、 Cortex-A55の既定のDomain ID（DID）は3 です。Cortex-M7とCortex-M33の既定DIDは、それぞれ4と2です。

一方、ご提示のSDK例ではM7を9、M33を8と定義しています。 A55–M7間の排他処理にA55のDID 3を使う前に、その例で使用するSystem Manager／TRDCの設定を確認してください。 また、ロック後の GATEn.GTFSM の読み出し値は DID + 1 です。読み出し値9はDID 8を示します。