2417373_en-US

[#1]

T2080NXE8MQB based custom board booting from SPI NOR Flash

Dear Community

I am currently facing issue regarding custom T2080 board bring-up. What basically I am doing is I have generated PBL (rcw) from QCVS according to my custom board. I have flashed that in the SPI NOR and set the DIP switches to boot from SPI NOR. But T2080 is unable to fetch from SPI NOR. same issue is coming in ccs console (core not responding) as of you. We haven't programmed the CPLD yet

rcw(pbl) has been attached .

Below is the ccs console error screen:

Scanning for available TAPs connected via USB.....

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+ Available Remote Connections
+
+ 1 - CodeWarriorTAP - 00:04:9f:07:e3:5a
+ 2 - CodeWarriorTAP -
+ 3 - EthernetTAP -
+ 4 - GigabitTAP -
+
+ x - Exit Script without Changes
+
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Specify connection:
1

Configuring TAP Interface....

Configured Connection: cwtap : 00:04:9f:07:e3:5a

TDO -----
|
* Device 0 IDCODE: 118E701D Device: FSL T2080 rev 2.x
|
TDI -----

###################################################
#
# configTAP - Redefine TAP interface
#
# scanboard - Scans the target system
# and returns the JTAG IDCode
#
# ir - Loopback test
#
###################################################

CCSAPI connection #1 accepted from activation.acronis.com at Wed Sep 30 10:26:35 2026
(bin) 2 % delete all
(bin) 3 % config cc cwtap
(bin) 4 % ccs::config_chain t2080
(bin) 5 % display ccs::config_chain t2080

(bin) 6 % display ccs::config_chain t2080

(bin) 6 % display ccs::get_config_chain
Chain Position 0: T2080
Chain Position 1: e6500 thread 0
Chain Position 2: e6500 thread 1
Chain Position 3: e6500 thread 0
Chain Position 4: e6500 thread 1
Chain Position 5: e6500 thread 0
Chain Position 6: e6500 thread 1
Chain Position 7: e6500 thread 0
Chain Position 8: e6500 thread 1
(bin) 7 % ccs::reset_to_debug
T2080: Core not responding

Re: T2080NXE8MQB based custom board booting from SPI NOR Flash

Hi

there is a typo of SPI being not used in a snap. It is used actually.
The thing is that we dont have direct access to IFC NOR & NAND. we only have access to SPI NOR via SPI protocol. and i first flashed rcw in the SPI NOR and then set the settings of dip switches accordingly. 

The error I posted earlier is after I have done above.

Re: T2080NXE8MQB based custom board booting from SPI NOR Flash

Hi,

Yes—cfg_rcw_src is the DIP-switch strap that selects where the T2080 boot ROM obtains the RCW. It does not contain the RCW contents itself; the RCW must already be programmed in the selected boot device.

According to your schematic:

• NOR flash boot: 0_0010_0111
• NAND flash boot: 1_0001_1001
• SD and SPI boot are marked not used.

Therefore, if your board boots from NOR flash, set cfg_rcw_src=0_0010_0111. If it boots from NAND flash, use 1_0001_1001. SW1 carries cfg_rcw_src0–7; SW2 switch 1 carries cfg_rcw_src8.

So, “hard-coded RCW” should more accurately mean that the RCW is fixed/programmed in the boot memory—not merely the DIP-switch setting.

Regards

Re: T2080NXE8MQB based custom board booting from SPI NOR Flash

what do you mean exactly regarding Hard coded RCW. Did you mean the setting of dip switches (cfg_rcw_src). If yes then what setting would be in my case.

I have attached the snap of dip switches from my schematics mentioning cfg_rcw_src.

Re: T2080NXE8MQB based custom board booting from SPI NOR Flash

Hello,

The JTAG connection is working—the TAP identifies the T2080 correctly. The failure occurs when CodeWarrior tries to release/reset the e6500 cores, so “Core not responding” points first to reset, clock, power, or an invalid boot configuration, not to the USB-TAP connection. 

Recommended bring-up sequence

1. Do not start with SPI boot. Configure the board for a valid T2080 hard-coded RCW mode and confirm the SYSCLK/DDRCLK strap values match the actual clocks. NXP recommends using hard-coded RCW during initial board bring-up because it excludes external RCW-device access.

2. With hard-coded RCW selected, run:

   delete all
   config cc cwtap
   ccs::config_chain t2080
   ccs::reset_to_debug
   

   If this still fails, inspect hardware rather than the PBL.

3. Verify with an oscilloscope:

   • PORESET_B
   • HRESET_B
   • COP_HRESET_B
   • COP_SRST_B
   • ASLEEP
   • RESET_REQ_B
   • SYSCLK and DDRCLK

   Confirm correct polarity, voltage levels, sequencing, and that HRESET_B is not being held active. Pay particular attention to the reset logic around the COP/JTAG header; incorrect reset ownership can prevent the debugger from placing the core in stop mode.

4. Check all required rails and clocks, especially processor core voltage, OVDD, GVDD, SVDD, and reference clocks. A valid JTAG ID alone does not prove that the core power, PLL, or reset sequencing is correct.

5. After hard-coded mode works, use CodeWarrior’s SRAM launch configuration to connect and load/override the RCW. NXP’s recommended flow is: validate hard-coded RCW, generate the custom RCW with QCVS, connect through SRAM, then program the RCW into flash.

6. Only then debug SPI NOR boot:

   • Confirm the DIP-strap encoding and sampling.
   • Verify SPI NOR voltage, reset, chip-select, clock, and IO wiring.
   • Read back the programmed flash and verify the image byte-for-byte.
   • Confirm the PBL is generated for the correct T2080 revision and SPI boot format.
   • Program it at the offset expected by the T2080 boot ROM; do not assume offset 0x0 without checking the boot mode/documentation.
   • Use a logic analyzer to verify that the processor asserts SPI chip select and clocks during POR.

Regards