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Could you please tell me the ip_clk frequency range for IFC interface of LS1021A?

Hi,

I can't find the  ip_clk frequency range for IFC interface of LS1021A in the spec such as datasheet, ARM and checklist. Could you please tell me it?

Jason_in_job_1-1790240479362.png


Thanks in advance!

Best regards!

Jason


QorIQ LS1 DevicesRe: Could you please tell me the ip_clk frequency range for IFC interface of LS1021A?

There is no separately specified minimum/maximum frequency range for IFC ip_clk on LS1021A . ip_clk is the internal IFC module clock , equal to the processor’s platform clock ; it is not an interface pin clock. The datasheet explicitly says that IP_CLK is internal and unavailable on the interface pins.

For the standard LS1021A clock configuration:

yipingwang_0-1790563851858.png

The reference manual describes the platform PLL as generating a 300 MHz platform clock , and a documented RCW example uses SYSCLK = 100 MHz with SYS_PLL_RAT = 3 , producing ip_clk = 300 MHz .

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