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2415886_en-US
2415886_en-US
Hi,
I'm validating the external active-tamper loop on the i.MX8DXL EVK (MCIMX8DXL-WEVK) via U-Boot.
From the board schematic, I've confirmed J20 (TAMPER header, 1x3) is wired as:
- Pin 1 = TAMPER_IN4 (net SNVS.TAMPER_IN4, ball AJ13)
- Pin 2 = GND
- Pin 3 = TAMPER_OUT0 (net SNVS.TAMPER_OUT0, ball AP22)
These are dedicated SNVS pins, not shared with SAI2/SAI3 like TAMPER_OUT1-4/IN0-3.
Available U-Boot commands: tamper_pin_cfg, snvs_cfg (with sub-registers hp.lock, hp.secvio_intcfg, hp.secvio_ctl, lp.lock, lp.secvio_ctl, lp.tamper_filt_cfg, lp.tamper_det_cfg, lp.tamper_det_cfg2, lp.tamper_filt1_cfg, lp.tamper_filt2_cfg, lp.act_tamper1_cfg through lp.act_tamper5_cfg, lp.act_tamper_ctl, lp.act_tamper_clk_ctl, lp.act_tamper_routing_ctl1, lp.act_tamper_routing_ctl2), snvs_sec_status, snvs_clear_status.
Since TAMPER_OUT0/TAMPER_IN4 form an active tamper pair, my questions:
1. Which lp.act_tamperN_cfg channel (1-5) corresponds to TAMPER_OUT0?
2. What values for lp.act_tamper_routing_ctl1/routing_ctl2 route TAMPER_OUT0's pattern to be checked against TAMPER_IN4?
3. What value for lp.act_tamper_clk_ctl enables the pattern clock for this channel?
4. What value for lp.act_tamper_ctl globally enables active tamper detection for this channel?
Goal: closing a jumper across J20 pins 1-3 should read as secure in snvs_sec_status, and opening it should trigger a violation.
Is there a reference test procedure or app note for external active tamper validation on i.MX8DXL?
Thanks!