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[#1]

i.MX93 power sequencing

I am designing a low power PCB based around the i.MX93 and its recommended PMIC (PCA9451).

The AN13917 power consumption measurement document suggests that in its lowest power mode (section 6.7.8) the SoC+DRAM power consumption should be ~174mW. However, the current measurements in the document are taken after the PMIC, so do not include any efficiency losses. 

When calculating the actual expected power consumption, the vdd_ana_0p8 rail stands out as a very high consumer of energy. The 16.5mA current draw on this rail causes 69mW dissipation in the PMIC LDO (from a 5V input). This is ~60% of the efficiency losses.

I would like to power this rail from a separate SMPS module (TI TPSM82821) to reduce these losses, however the i.MX93 datasheet has no definition of Tstep or Toff_step in the power rail sequencing requirements. Are there actually any timing requirements, or only sequencing?

Would it be sensible to use VDD_SOC as the enable trigger (via a comparator) for the external SMPS, or are there better options to use? I'm assuming that the 0V8 will discharge faster than VDD_SOC during power down as the TPMS82821 has an output active discharge function.

Re: i.MX93 power sequencing

Hello,

There is a time for Tstep or Toff_step in Table 6. PWRUP mode:

tSTEP (Time to next power rail ON from prev rail POK):  2 ms

tOFF_STEP (Time to next power rail off from prev rail off): 8 ms

Also, you can use VDD_SOC as reference to trigger external regulator in power-up/power-off sequences.

Best regards.