2414120_en-US

[#1]

T1042 DDR4 Initialization Failure

I have a T1042 design using 64-bit interface to DDR4.  We already found an issue with an improper bit swap between nibbles in the uppermost byte of the interface which we know cannot be compensated for in SW settings.  We are going to implement a fix in a PWB revision.  However since the rest of the bits are correct and the swapping falls into what is allowed according to the reference manual we are hoping to instead operate in 32-bit mode so that we can still proceed bringing up SW and the rest of the design.  I have tried this using QCVS DDR validation tool, however I cannot get the memory to initialize.  I have input the parameters of the device and made sure to set the DQ mapping values according to my design for DQ[0:31] however I continue to get bit ACE= 1 in the ERR_DETECT register.  The processor is getting the RCW via SPI interface and the DDR frequency is set to 800MHz.  Is there a way to use CodeWarrior/QCVS to verify it received the correct RCW value?  What are some other settings to consider for 32-bit mode operation that could explain why it is not working?  I would greatly appreciate any support.  Thank you.

QorIQ T1 DevicesRe: T1042 DDR4 Initialization Failure

  Is there a way to use CodeWarrior/QCVS to verify it received the correct RCW value? 

[A] Yes, that's possible, you could connect the CCS, and read out the DCFG_CCSR_RCWSR1-DCFG_CCSR_RCWSR16 to compare with the RCW in the SPI flash.

What are some other settings to consider for 32-bit mode operation that could explain why it is not working?

[A]Is it discrete DDR4? For the generally rule, please refer to  QCVS_DDR_User_Guide.

For the HW design, please refer to the

AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

Thanks

Re: T1042 DDR4 Initialization Failure

Hello June,

Thanks for the reply.  I was able to use CCS to read the RCW status registers and confirm the RCW is programmed as expected.

I am using discrete DDR4 and have been through the user guide and layout considerations.

I have confirmed that we have a 650MHz clock for operation at 1300MT/s to satisfy Errata A-007864 for using a 32-bit interface.  A colleague suggested checking that the chip select is toggling.  I found that once the QCVS tool starts sending the configuration to the processor, the CS0 signal is held sufficiently low.  After programming is complete and it attempts to run the validation routine the CS0 signal is no longer being fully asserted.  I independently using a JTAG boundary scan tool to confirm that the signal is connected as expected and that the T1042 I/O can drive the net low enough to satisfy the VIL for the DDR4 memory device.  I also confirmed the net looks good in terms of routing for signal integrity and that it is not shorted to anything.  It seems that there is something about the memory controller configuration that is not allowing the chip select signal to function correctly.  Any other ideas?  Thank you.