Introduction
Based on ES_PN7642 , the PN7642 operating in ULPCD mode may, in very rare cases, enter an unresponsive state.
This is caused by very strong distortion of the power supplies or GND of the IC during this boot-up time can cause a loss of the internal reset state and the boot-up sequence gets stuck.
This article describes method for evaluating whether a design is sensitive to this phenomenon and provides guidance on how to monitor it.
The primary indicator is the LFO (Low-Frequency Oscillator). In particular, instability of the LFO during the ULPCD "Active" period may indicate an increased risk of the device entering the ULPCD Freeze (unresponsive) state.
This LFO instability may be caused by external events, such as ESD (Electrostatic Discharge), or by interference from other electronic circuits integrated on the PCB.
LFO instability is characterized by deviations in the oscillator's duty cycle and/or the occurrence of missing LFO cycles.
1// Where to measure the LFO ?
The measurement is done during the ULPCD "Active" phase
Tomas_Parizek_0-1789453318198.pngTomas_Parizek_0-1789453318198.pngTime window where to measure the LFO stability
Tomas_Parizek_2-1789453587804.pngTomas_Parizek_2-1789453587804.png
Detail of the "LFO" Start. Please start the measurement when the LFO frequency gets stable.
Tomas_Parizek_3-1789454620348.pngTomas_Parizek_3-1789454620348.pngAt the end of the ULPCD active phase, the last LFO clock cycle typically exhibits a slight deviation. This behavior is expected and should not be interpreted as an indication of LFO instability.
Tomas_Parizek_4-1789454768289.pngTomas_Parizek_4-1789454768289.png
2// How to enable LFO observability
The LFO can be routed with the help of ULPCD test buses on GPIO2.
For firmware versions up to PN7642 FW v03.01. -> AN14518 (5.4 How to use test signals for PN7642)
- Write xx before entering ULPCD mode
For firmware versions from PN7642 FW v03.01 onward -> PN7642 Datasheet (9.14.3.17.12 ULPCD_TESTBUS_MUX_SETTINGS (0702))
- Write xx before entering ULPDC mode