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2413117_en-US

2413117_en-US

S32K396 SELCTL update to PLL from FIRC

Using the S32K396-BGGA-DC1 dev board, I'm trying to use the 16MHz External Oscillator (Y2) for clocking.

I'm running into issues when I set the SELCTL of the MC_CGM Mux 0 CSC to PLL then set CLK_SW = 1. I get a debug error (Trace32) and the code running crashes. I did attempt to run without a debugger connected, with one of the user LEDs to turn on after it gets past setting CLK_SW = 1. The LED never turns on so I am at the assumption the micro gets hung up in the same spot.


Here is the psuedo code of my clocking configuration:

PLLCR.PLLPD = 1 

Set PLLDV.MFI, PLLDV.RDIV, PLLDV.ODIV2, and PLLODIV[0].DIV

PLLCR.PLLPD = 0

Confirm PLLSR.LOCK = true (while loop)

PLLODIV[0].DE = 1

Configure flash wait times to 160MHz and RAM      // Based on A+ Mode config

MUX[0].DIV_TRIG_CTRL.TCTL = 1

MUX[0].DIV_TRIG_CTRL.HHEN = 1

Configure MUX[0].DC[0 - 7] with respective clk divider values

MUX[0].DIV_TRIG = 1

Wait until DIV_STAT = 0

MUX[0].CSC.SELCTL = 0x8 (PLL_PHI0_CLK)

MUX[0].CSC.CLK_SW = 1           << Crashes here on attempt to write to 1


Am I missing something in my procedure? I made sure to be below limits of the individual dividers, so I do not think that is the issue. Thanks ahead of time for any guidance on this!

Re: S32K396 SELCTL update to PLL from FIRC

Found the issue, was needing to set SAFE_SW = 1 before setting SELCTL.

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