We have a requirement here, which is for two S32k388s to communicate with each other using SPI communication. Can either one be the master or slave? For example, when I use chip A as the host, the I item in the IOMUX table describes the host input of MISO. If chip A is used as a slave, does this O term describe the slave output of MISO? The pins in our current project are fixed. For example, SOUT: PTA18+GPIO_ALT_FUNC_4 is used on MOSI, SIN: PTA20+239+GPIO_ALT_FUNC_4 is used on MISO. This is based on the current host mode we are using. Can it still work normally when switching to slave mode without changing the pins? Is it sufficient to switch slave mode by simply changing the HRDIR of CFGR0 and the MASTER of CFGR1?
Hello @xlele ,
You do not need any hardware changes to switch between master and slave mode.
In a standard two-chip SPI setup, the pins are always cross-connected between the two devices:
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Chip A SOUT → Chip B SIN (MOSI line)
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Chip A SIN ← Chip B SOUT (MISO line)
The SOUT pin is always a serial data output and SIN is always a serial data input, regardless of whether the device is operating as master or slave. So when Chip A switches to slave mode, its SIN (PTA20) still correctly receives data from the new master and its SOUT (PTA18) still correctly drives data back — no rewiring needed.
Regarding the register changes:
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CFGR1[MASTER] = 0 — this is the key bit to switch the module into slave mode.
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CFGR0[HRDIR] — this bit controls the direction of the HREQ (Host Request) pin, which is multiplexed with PCS[1]. It has no effect on the SOUT/SIN data lines. In slave mode, HRDIR can be set to 1 (output) so that the slave drives the HREQ pin to signal the master that it has data ready to transmit. Note that on S32K388, there is no dedicated external LPSPI_HREQ pin — the host request function uses the LPSPI_PCS[1] mux (enabled via CFGR0[HREN]). If you are not using the host request feature (CFGR0[HREN] = 0), HRDIR is not relevant to your use case and CFGR1[MASTER] alone is sufficient.
Best regards,
Pavel