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2412755_en-US

S32K322 and S32K312 : Queries Regarding CMU Interrupts, Reset Reaction, and Detection Latency
  • Could you please provide the mapping of failure events to the respective CMU instances (CMU0, CMU1, and CMU2)?
    The interrupt documentation lists a total of seven interrupts, but it is not clear which failure events are handled by each CMU instance and their corresponding failure actions. 
    Please see attached images system clock monitoring.pngsystem clock monitoring.pngsystem clock monitoring.pngInterruptmapping.pngInterruptmapping.pngInterruptmapping.png

  • What is the exact meaning of the "Reset Reaction Interrupt"?
    Does this interrupt get generated prior to a destructive reset, allowing software intervention before the reset occurs?

  • The clock monitoring latency can be configured from 1 µs to 1 ms.
    Does selecting a lower latency effectively reduce the debounce/filtering time and make clock failure detection more sensitive or faster?

Re: S32K322 and S32K312 : Queries Regarding CMU Interrupts, Reset Reaction, and Detection Latency

Hi@WadkarY

1.Could you please provide the mapping of failure events to the respective CMU instances (CMU0, CMU1, and CMU2)?

image.pngimage.pngimage.pngimage.pngimage.pngimage.png

As can be seen, only CMU_FC_0,CMU_FM_1,CMU_FM_2 is configurable as an interrupt; the others should be treated by default as sources of a destructive reset, rather than as standard CMU interrupts.

CMU_FC_0->CMU0

CMU_FM_1->CMU1

CMU_FM_2->CMU2

CMU_FC_3->CORE_CLK_FAIL CMU reset reaction interrupt

CMU_FC_4->AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt

CMU_FC_5->HSE_CLK_FAIL CMU reset reaction interrupt

CMU_FC_6->CM7_CORE_CLK_FAIL CMU reset reaction interrupt


2.Does this interrupt get generated prior to a destructive reset, allowing software intervention before the reset occurs?

No, expect destructive reset behavior unless the MC_RGM/DCM destructive-reset interrupt bypass is deliberately configured

for example:

1.CMU_FC_4 detects AIPS_PLAT_CLK frequency exceeding the threshold
↓ 

Destructive Reset asserted + IRQ 215 issued simultaneously
↓ Almost instantaneously

MCU reset → Restart from Reset Vector

Software reads MC_RGM.DES[AIPS_PLAT_CLK_FAIL] to identify the reset cause


3.Does selecting a lower latency effectively reduce the debounce/filtering time and make clock failure detection more sensitive or faster?

This parameter is related to REF_CNT.

•Higher values of RCCR[REF_CNT] results in longer measurement window, leading to better accuracy in monitored clock check.


•Lower values of RCCR[REF_CNT] results in shorter measurement window, leading to faster FHH and FLL event response, but higher inaccuracy in reported result.

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