2411799_en-US

Yes

Drive capability for RGMII interface of LS1021A

Hi,

I have another question:

On my board, eTSEC1 and eTSEC3 of LS1021A will be configured as RGMII mode to driver PHY. But the size of my board is very big, I'm afraid that the too long trace on PCB(about 200到250mm) will cause insufficient drive capability for RGMII interface(250Mbps per data signal) . Could you please provide the route constraint for RGMII interface, especially trace length on PCB based on common FR-4 PCB(Dk 4.2~4.4, Df 0.022)? Cause, I can't find any PCB design consideration on NXP website. Also AN4878_Design Checklist only show the design requirement of schematic.

Thanks in advance!

Best regards!

Jason

QorIQ LS1 Devices

Re: Drive capability for RGMII interface of LS1021A

Yes, 100 mm is typically a good and conservative RGMII routing target.

Please also verify the RGMII timing/skew and PHY internal-delay configuration.

Re: Drive capability for RGMII interface of LS1021A

Hi, yiping:

so, typically 100mm length could be guaranteed drive capability for RGMII interface, right?

Thanks in advance!

Best regards!

Jason

Re: Drive capability for RGMII interface of LS1021A

NXP evidence does not give an LS1021A-specific max RGMII length, but 200–250 mm is longer than the related 6-inch QorIQ guideline, so use ≤150 mm where possible or require IBIS-based SI/timing verification.

Please refer to this application note:

https://www.nxp.com/docs/en/application-note/AN13335.pdf

Here are some general PCB layout guidelines commonly applied to RGMII interfaces on FR-4 material (Dk 4.2–4.4):

Trace length: For RGMII at 125 MHz (DDR, effectively 250 Mbps per signal), the recommended maximum trace length is typically 100–150 mm for standard designs. A trace length of 200–250 mm is on the longer side and may introduce signal integrity concerns such as increased propagation delay, reflections, and potential setup/hold timing violations.

- Consider using a PHY with adjustable internal delay (RGMII-ID mode) to compensate for skew introduced by long traces.

- If trace lengths must exceed 150 mm, controlled impedance (50 Ω single-ended) and careful length matching within the data bus (±5 mm intra-pair skew) are strongly recommended.

Impedance control: Target 50 Ω single-ended for all RGMII signals on FR-4.

Clock-to-data skew: Keep clock-to-data skew within ±500 ps as per the RGMII specification.

Series termination: Adding a 22–33 Ω series resistor near the driver output can help dampen reflections on longer traces.