2411764_en-US

S32R264 – CLK_OUT0 (CLKOUT) limitation to 60 MHz, can I output 80 MHz?

#S32R2X

I am using S32R264. I have a question about CLK_OUT0 (Figure 6-3 shows CLKOUT selection via MCB_CLKOUT_SEL in RM) and the possibility to output SDPLL_CLK80/AFEPLL_CLK80 at 80 MHz on this pin.

However, Table 5‑3 ("Maximum system level clock frequencies") says the max frequency for CLK_OUT[01] is 60 MHz, with no explanation for this restriction.

I noticed only one output has a CMU attached – maybe that's the reason, but I don't use CMU.

I need to provide 80 MHz to an external Frontend board that generates Chirp, and I want a single clock source for everything.

Currently I have two separate 100 MHz oscillators (CWX813‑040.0M for MCU, CWX813‑100.0M for Frontend). I suspect that even good independent oscillators may degrade signal quality due to lack of phase alignment. My waveform generation runs from the 100 MHz clock, while the AFE inside MCU runs from 40 (320) MHz. I would like to switch waveform generation to 80 MHz and take that clock from MCU, so the whole system is synchronous and in phase.

Is it possible to output 80 MHz on CLK_OUT0 if CMU is disabled?

What is the real reason for the 60 MHz limit?