Hi Expert,
We are planning to implement IEEE 1588/PTP time synchronization on the PFE Ethernet interfaces of our custom S32G274A board.
Our current software configuration is:
- SoC: NXP S32G274A
- Board: Customer board based on S32G274A
- Operating system: QNX 7.1
- PFE driver: PFE-DRV_S32G_A53_QNX 1.9.0, io-pkt version
- PFE firmware: PFE-FW_S32G 1.12.0
- PFE interfaces under test: PFE EMAC0 and PFE EMAC2
- PFE EMAC1 is not included in the current test because the firmware of its external AQR113C PHY has not yet been programmed.
We checked the PFE driver source code and found that it contains IEEE 1588 support and implements the following QNX driver-specific PTP commands:
- PTP_GET_TIME
- PTP_SET_TIME
- PTP_GET_TX_TIMESTAMP
- PTP_GET_RX_TIMESTAMP
- PTP_SET_COMPENSATION
- PTP_GET_COMPENSATION
The current default build configuration disables this feature:
PFE_CFG_IEEE1588_SUPPORT=0
PFE_CFG_IEEE1588_I_CLK_HZ=0
PFE_CFG_IEEE1588_EMAC0_O_CLK_HZ=0
PFE_CFG_IEEE1588_EMAC1_O_CLK_HZ=0
PFE_CFG_IEEE1588_EMAC2_O_CLK_HZ=0
Our startup code already enables the PFE_TS clock through SCMI, but we have not yet configured the IEEE 1588 input and output clock frequencies in the PFE driver.
Could you please provide guidance on the following questions?
1. Does PFE EMAC0/EMAC1/EMAC2 on S32G274A officially support IEEE 1588 hardware TX and RX timestamping with PFE-DRV 1.9.0 and PFE-FW 1.12.0 on QNX 7.1?
2. What is the expected SCMI PFE_TS clock frequency on S32G274A?
3. What values are recommended for the following build parameters?
PFE_CFG_IEEE1588_I_CLK_HZ
PFE_CFG_IEEE1588_EMAC0_O_CLK_HZ
PFE_CFG_IEEE1588_EMAC1_O_CLK_HZ
PFE_CFG_IEEE1588_EMAC2_O_CLK_HZ
4. Do all three PFE EMACs share the same PTP hardware clock, or does each EMAC have an independent PTP system-time counter?
5. Which PTP transport modes are supported by this driver?
- Layer-2 PTP, EtherType 0x88F7
- UDP/IPv4
- UDP/IPv6
- One-step timestamping
- Two-step timestamping
- End-to-End delay mechanism
- Peer-to-Peer delay mechanism
6. Does enabling PTP require any additional PFE firmware configuration, firmware feature, FCI configuration, or startup initialization?
7. Is there an NXP- or QNX-recommended user-space PTP daemon or sample application for this PFE driver? The current driver exposes PTP functions through netdrvr/ptp.h and SIOCGDRVSPEC/SIOCSDRVSPEC, rather than a Linux-style /dev/ptpX PHC device.
8. Are there any known errata, limitations, or required initialization sequences related to:
- PFE timestamp clock initialization;
- TX/RX timestamp delivery through HIF;
- timestamp compensation;
- simultaneous PTP operation on multiple PFE EMACs?
If available, could you also provide a reference configuration, sample application, or validation procedure for IEEE 1588 on S32G274A PFE under QNX?
Thank you for your support.
BR,
Waitewang
Hello Expert
Thank you for the detailed information. We have verified that the PTP time and compensation interfaces work correctly on PFE0 and PFE2 with PFE-DRV 1.9.0 and PFE-FW 1.12.0.
Before closing this NXP PFE support case, could you please clarify three S32G274A-specific points?
1. We are currently using PFE_CFG_IEEE1588_I_CLK_HZ = 200 MHz and 50 MHz output clocks for the enabled EMACs. Is this configuration officially supported and recommended?
2. Does each PFE EMAC have an independent IEEE 1588 timer, or can an EMAC be configured to share the time base from another EMAC?
3. Where is the required 400 MHz XBAR clock configured, and which register or runtime indication can be used to verify it?
Hi,waitewang
Thank you for contacting us. The following information is hoped to be helpful to you!
1. The IEEE 1588 timestamping feature (AAVB-2500) was first introduced in BETA_0.9.0. Note that the original record is [PFE_QNX_DRIVER] Add IEEE1588 timestamping support. (Refer to PFE-FW_S32G_1.12.0_ReleaseNotes.pdf.) Your software version compatibility meets the requirements.
2. The clock of PFE_TS is provided by GMAC_TS_CLK, with a range of 5-200 MHz. The minimum value needs to be determined based on the set mode.
3. It needs to be set according to the value of GMAC0_TS_CLK. Refer to the following content.
4. Yes, you can refer to the following figure.
5. From the code and documentation infromation, technically PTP uniformly identifies the transport layer, supporting (UDP/IPv4, UDP/IPv6, Layer-2 PTP), support theTwo-step and E2E/P2P.
6.Please note the following:The XBAR clock set to 400 MHz for timestamping feature to work reliably, refer to S32G Reference Manual.The PFE_CFG_IEEE1588_EMACn_O_CLK_HZ value must be less than PFE_CFG_IEEE1588_I_CLK_HZ. Before driving the loading process, it is necessary to confirm the following: All relevant clocks, power/reset, and pins of PFE have been configured according to the S32G RM, and the firmware binary s32g_pfe_class.fw has been deployed to the target board.
7. We apologize that NXP does not provide a ready-made PTP daemon or sample application for the QNX PFE driver.
8. Please refer to the following contents in the attached documents:
PFE-DRV_S32G_QNX_1.9.0_ReleaseNotes.pdf/4 Known Issues
PFE-DRV_S32G_QNX_1.9.0_UserManual.pdf/5.2 Limitations
PFE-DRV_S32G_QNX_1.9.0_UserManual.pdf/5 Usage
We do not currently provide dedicated application examples. It is recommended to refer to the relevant information in the following documents.(PFE-DRV_S32G_A53_QNX_1.9.0\doc)
BR
Joey
Hi,waitewang
Thank you for your reply.
1.For the input clock, the 100Mhz was suggested according to the S32G RM.The PFE_CFG_IEEE1588_EMACn_O_CLK_HZ value must be less than PFE_CFG_IEEE1588_I_CLK_HZ.
2.PFE EMACs support two timestamping modes, Internal Timestamp Mode and the External Timestamp Mode. The detail information you can refer to the PFE-DRV_S32G_QNX_1.9.0_UserManual.pdf of chapter 6.4.1 Configuring and enabling the IEEE1588 timers.
3.The XBAR clock will be configured in the ATF; you can try to use the commend of "clk dump" in uboot to check it.
Hope this information can help you.
BR
Joey