2410834_en-US

[#1]

Could you please provide me the pin delay of LS1021AXE7KQB?

Hi，

Currently, I'm designing PCB for my board. For critical timing requirement of DDR4 interface, I need to compensate the pin delay difference in the  LS1021AXE7KQB package on the PCB. So, could you please provide me the pin delay information of LS1021AXE7KQB?

Thanks in advance!

Best regards!

Jason

QorIQ LS1 DevicesRe: Could you please provide me the pin delay of LS1021AXE7KQB?

All internal die to pad wires of the DDR4 interface are length matched within the package, so the layout trace length task is to be done between processor's and SDRAM's pins. No specific package delay values were provided as they are not needed for the design approach.

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

Hi，yiping

For DDR4 interface of LS1021A, is it necessary to compensate pin delay difference in the package on the PCB? 

Thanks in advance!

Best regards!

Jason

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

The requested documents are NXP Confidential Proprietary and can only be provided under non-disclosure agreement (NDA).

Did you sign NDA with NXP? If yes, would you please provide your NDA copy or your NDA number?

You could sing a new NDA from https://www.nxp.com/webapp-signup/ndaReqForm

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

Asked for the required information from the AE team.

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

Hi,

Any response is welcome!

Thanks in advance!

Best regards!

Jason

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

Hi, yiping：

Get it, many thanks to you!!!

BTW, I have another question.  eTSEC1 and eTSEC3 of LS1021A will be configured as RGMII mode to driver PHY. But the size of my board is very big,  I'm afraid that the too long trace on PCB will cause insufficient drive capability for RGMII interface(250Mbps per data signal) . Could you please provide the route constraint for RGMII interface, especially trace length on PCB based on common FR-4 PCB(Dk 4.2~4.4, Df 0.022)? Cause, I can't find any PCB design consideration on NXP website.  Also AN4878_Design Checklist only show the design requirement of schematic.

Thanks in advance!

Best regards!

Jason

Re: Could you please provide me the pin delay of LS1021AXE7KQB?

Would you please create a new thread for your new question?

Thanks.