For the LX2080A We need to disable 4 out of the 8 cores. Could you please tell me how to turn off core for specific 4 of the 8 cores?
For testing, I added the following to the rcw_2200_750_3200_19_5_2.rcw file, but it will not boot.
.pbi
write 0x01e00094, 0x00000f0
.end
Is there anything else that needs to be modified?
If the intent is to keep the first four LX2080A clusters active and disable the upper four active cores, use the physical-core bitmap:
Copy
# Disable physical cores 8, 10, 12, 14
.pbi
write 0x01e00094, 0x00005500
.end
We applied it. But it didn't boot.
.pbi
write 0x01e60060,0x0000000f
write 0x01e00094,0x000000f0
.end
So, with the version not applied, I read the registers from the uboot prompt as follows.
It appears that the active core is an odd number.
> md.l 0x01e00094
01e00094: 00000000 00000000 00000000 00000000 ................
01e000a4: 87360220 00000040 00000000 00000000 .6.@...........
=> md.l 0x01e60060
01e60060: 0000aaaa 00000000 00000000 00000000 ................
01e60070: 00000000 00000000 00000000 00000000 ................
Could this be the cause?
Thanks
Your target register is correct for disabling cores, but I would not leave the change as only:
.pbi
write 0x01e00094, 0x00000f0
.end
Use a full 32-bit value and make sure the boot/release path does not try to start the disabled cores:
.pbi
write 0x01e00094, 0x000000f0 /* COREDISR: disable cores 4,5,6,7 */
.end
0x01e00094 is DCFG + 0x94 ; the LX2160A/LX2080A RM lists DCFG base address = 0x1E0_0000 and COREDISR at offset 0x94 . COREDISR is the documented mechanism for disabling/clock-gating unused physical cores, and it can be programmed before system ready by PBI . Bits/fields for cores 4–7 correspond to Core 4 Disable through Core 7 Disable, so 0x000000f0 is the expected mask if you want to keep cores 0–3 and disable cores 4–7 .
The important additional item is boot release. For an LX2/LS2 4-core case, the documented/internal guidance is to pair:
Boot Release @ 0x01e60060 = 0x0000000f
COREDISR @ 0x01e00094 = 0x000000f0 /* disable Core7:4 */
so only cores 0–3 are released for boot, while cores 4–7 are disabled . The Boot Release Register BRRL is at RST base 0x1E6_0000 + 0x60 , and its bits CR0...CR15 release the corresponding cores from boot holdoff . Also verify that the primary boot core is not included in your COREDISR mask; the RM says the boot core can be identified through BRCORENBR[CORE_NBR] .
Two practical checks for the boot failure:
After boot, confirm the result by reading COREDISR and the core-disable status register; an LX2 experiment used COREDISABLESR @ 0x01E00990 to confirm the disabled-core mask . Also note that cores disabled through COREDISR must not be re-enabled by software later .
For “keep cores 0–3, disable cores 4–7,” use COREDISR = 0x000000f0 and make sure the boot-release mask releases only the active cores, e.g. BRRL = 0x0000000f ; otherwise firmware may try to start a core you have disabled.
The core numbering in the LX2160A is sequential with respect to the cluster groups. The 16 cores are arranged in 8 clusters, with each cluster containing two cores. The numbering is as follows:
Cores 0 and 1 are in Cluster 1
Cores 2 and 3 are in Cluster 2
...
and so on, up to Cores 14 and 15, which are in Cluster 8
Disabling all cores within a cluster causes system to hang. So it is impossible to achieve your purpose.
Please try the following configuration.
.pbi
write 0x01e00094,0x0000aa00
write 0x01e60060,0x000000aa
.end
It seems that disabling all cores within a cluster causes system to hang.
Let's only disable one core in one cluster.
.pbi
write 0x01e00094, 0x00008888
write 0x01e60060, 0x00002222
.end
.pbi
write 0x01e00094,0x00005500
write 0x01e60060,0x000000aa
.end
We applied it. However, it did not boot.
Are there any other things to look into?
It boots up, but the result is as follows.
=> md.l 0x01e00094
01e00094: 0000aa00 00000000 00000000 00000000 ................
01e000a4: 87360220 00000040 00000000 00000000 .6.@...........
=> md.l 0x01e60060
01e60060: 0000aaaa 00000000 00000000 00000000 ................
01e60070: 00000000 00000000 00000000 00000000 ................
The kernel also detects 8 CPUs.
Can you test this on the LX2080a?
Thanks,
The results seem to be the same.
=> md.l 0x01e00094
01e00094: 00008888 00000000 00000000 00000000 ................
01e000a4: 87360220 00000040 00000000 00000000 .6.@...........
=> md.l 0x01e60060
01e60060: 0000aaaa 00000000 00000000 00000000 ................
01e60070: 00000000 00000000 00000000 00000000 ................
The following settings seem correct.
.pbi
write 0x01e00094, 0x00005500
write 0x01e60060, 0x000000aa
.end
Regarding the value `0x0000aaaa` in the `0x01e60060` release register, I think that cores 1, 3, 5, 7, 9, 11, 13, and 15 are the disabled ones (indicated by 1), while cores 0, 2, 4, 6, 8, 10, 12, and 14 (indicated by 0) are the active cores actually supported by the LX2080A.
there is one core connected to each of the eight clusters, four clusters must be disabled; this leaves four active cores—one in each of the remaining four clusters. but even after modifying `COREDISR`and `BRRL`, the `BRRL`and `COREDISABLESR` register continues to show `0x0000aaaa`.
So, I checked the SoC initialization routine in `atf/nxp/soc-lx2160/soc.c`—where the cluster count was initially set to eight—and successfully booted the system after changing the cluster number to four. Currently, I have hardcoded the value to 4 within `get_num_cluster()`, but I hope that any other suggestions or feedback.
=> md.l 0x01e00094
01e00094: 00005500 00000000 00000000 00000000 .U..............
=> md.l 0x01e60060
01e60060: 0000ffaa 00000000 00000000 00000000 ................
=> md.l 0x01e00990
01e00990: 0000ffaa 00000000 00000000 00000000 ................
Thanks,