2409517_en-US

[#1]

FIT Exception Issue MPC5777c

Hi Team, 

I am trying produce FIT exception.

        asm("li r0, 0x8000");

        asm("mtspr TCR, r0");

        asm("mtspr TCR, r0");

However, after executing this code, the board resets then enters the FIT exception handler. Could you please let me know if any additional configuration or changes are required to correctly trigger and handle the FIT exception?

Thank you for your support.

Best regards,
Pavan

Re: FIT Exception Issue MPC5777cHi,

IVPR points to a valid exception vector table
yes.

IVOR10 is configured for the FIT handler.
No. configured to IVOR11.

Interrupts are enabled (MSR[EE] = 1).
yes. BSP_MSR_Normal: Unsigned_32 :=16#02009000#;

The time base/FIT source is running.
yes.

You can find the details. which i configured help me out anything else i need to do

Regards,
PavanRe: FIT Exception Issue MPC5777cHi

MTSPR(IVOR10, entDECR'Address); -- Decrementer (handled by Ada runtime)
-- Now use e200/MPC55xx mapping
MTSPR(IVOR11, ent0B'Address); -- Fixed Interval Timer.. This will work by making IVOR10 as FIT.

Regards,
PavanRe: FIT Exception Issue MPC5777c

Hello,

The FIT exception should work once the exception infrastructure is properly configured.

Please verify:

• IVPR points to a valid exception vector table.
• IVOR10 is configured for the FIT handler.
• Interrupts are enabled (MSR[EE] = 1).
• The time base/FIT source is running.

Since the board resets before reaching the FIT handler, please also check the RGM reset status registers to identify the reset source.

Reference: FIT exception generation is described in AN2865 Section 3.

Best regards,
Peter

Re: FIT Exception Issue MPC5777c

Hello, 

I’d first check that the FIT enable bit in the TCR is set correctly and that the corresponding exception vector is properly initialized. Also make sure the exception/MSR configuration allows the FIT interrupt to be taken.

One thing that stands out is writing the same value to TCR twice:

asm("li r0, 0x8000");
asm("mtspr TCR, r0");
asm("mtspr TCR, r0");

If your intention is simply to force the FIT event, you may not need the second write. The exact behavior also depends on the PowerPC core and the TCR bit definitions for that specific device. 

Re: FIT Exception Issue MPC5777c

Hello,

Thank you for the update. Since you are using FIT, IVOR11 is the correct vector. Please additionally verify:

• TCR[FIE] = 1 (FIT interrupt enabled)
• FIT period selection (TCR[FP])
• TSR[FIS] becomes set when the FIT interval expires
• The FIT handler clears TSR[FIS]
• IVOR11 entry in the exception table contains the correct branch to the FIT ISR
• RGM reset status registers to determine whether another exception or reset occurs before entering the FIT handler

The value of TSR is particularly important. If TSR[FIS] is set but the ISR is not entered, the FIT is being generated but the exception dispatch path is not functioning correctly.

Best regards,

Peter

Re: FIT Exception Issue MPC5777cHello,

MTSPR(SPR_HID0, 16#00004000#); -- Enable TB status
MTSPR(SPR_TCR, 16#04800000#); -- Enable DEC +FIT
MTSPR(SPR_TSR, 16#04000000#);
i think is this correct iam enabling properly