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The larger the CCLK for LPC1778 IAP programming, the slower the programming speed.

Hello, when I was using the IAP mode of the LPC1778 to burn the program, I found that the larger the CCLK, the slower the burning process became.

Most IAP instructions can accept the CCLK parameter, which is described in the manual as: Param3: CPU Clock Frequency (CCLK) in kHz.

When debugging the LPC1778, I changed the default CCLK value of the driver from 12000 (12MHz) to 4000 (4MHz), and found that the burning speed actually increased. I tried several values and found that the larger the CCLK parameter, the slower the burning process. What could be the reason for this? What frequency does CCLK refer to?

回复： LPC1778 IAP烧录CCLK越大反而烧录越慢

Hi @BianHaopeng1

In the LPC1778/LPC178x documentation, CCLK refers to the ARM processor clock frequency / Main CPU clock, which is the core CPU clock. The IAP erase command explicitly requires the CPU Clock Frequency (CCLK) to be passed in kHz.

The reason is most likely not that "a lower CCLK results in faster physical Flash writes," but rather that the IAP ROM routine treats the CCLK you pass in as the current CPU frequency to calculate the Flash erase/write timings/wait times. Therefore, if the actual CPU is still running at a higher frequency, and you only change the parameter passed to IAP from 12000 to 4000, IAP will generate a shorter latency/timing based on 4 MHz, resulting in faster burning; however, this means that an incorrect clock is being passed to IAP, and the reliability of Flash erase/write, temperature/voltage boundaries, and long-term stability are not guaranteed.

The correct approach is to fill in the actual CPU clock speed at the time of the IAP call, in kHz, for the CCLK parameter.

BR

Harry

Re: LPC1778 IAP烧录CCLK越大反而烧录越慢

On the LPC1778, CCLK means the actual CPU core clock frequency (in kHz), not the crystal/XTAL frequency. The IAP bootloader uses the CCLK parameter to calculate its internal timing, particularly for flash programming and UART communication. If the value you provide does not match the MCU’s real CPU clock—or if the clock is configured differently from what the IAP code expects—the timing calculations can become incorrect, causing slower programming or communication. Therefore, make sure the CCLK parameter exactly matches the CPU clock after PLL/divider configuration (e.g., 120 MHz should be specified as 120000 kHz, not 12000).