2407439_en-US

[#1]

S32K146 SRAM ECC auto-correcting on SRAM read?

I am using S32K146. On cold start I write the 32-bit value 0 to all SRAM (to initialise the associated syndrome bits).

I have been under the impression that if I read an SRAM location and ECC detects a single-bit corruption then the ECC system will return the corrected value to the MCU and also correct the SRAM location by writing back to the SRAM location. Someone else at work has suggested that that is not the case stating "The corrected value is delivered to the MCU but the flipped bit remains in SRAM until it is rewritten".

Who is correct? If the other person, then where do I retrieve the corrected value from to then write it back to SRAM? Would this be using the ERM single-bit error interrupt? I can see the EARn register indicates the faulty SRAM address but no EDRn (?) register with the corrected value.

Either way, I just need to know how to correct the SRAM location if a single-bit error is detected. I am hoping that it is automatically done just by reading the location. If so, I can effectively ignore single-bit corrections as though they never existed, only using the interrupt to count up total number of corrections just for curiosity. This would also mean that I can perform a "read all of SRAM in slices" as part of my CBIT activities and so automatically fix any single-bit errors fairly quickly before a second corruption occurs and potentially making a double-bit unrecoverable error.

I notice that in the S32K1xx reference manual section 32 "PRAMC" mentions auto-corrected SRAM but the PRAMC is not available on an S32K146. I notice it also mentioned single-bit ECC errors are automatically corrected in section 35.1.3.1 but this is for NVM, not SRAM. I could not find any explicit mention in the reference manual for S32K14x that reading an SRAM location with a single-bit error will result in the corrected value being returned to the MCU and the corrected value being written back to the SRAM location. Is there such a reference manual section?

I notice AN12522 rev 0 section 2.3 mentions detection and reaction times. I am taking the picture to indicate the single-bit fault occurring (the lightning arrow) but it is only detected some time later (fault detection time, on the first read of that location) and then corrected (fault reaction time). It is not clear if the reaction (correcting) occurs "invisibly" to the MCU, i.e. automatically fixed the SRAM location (write) and return the fixed value to the MCU (on the data bus).

Thanks

Darren