2407091_en-US

[#1]

MPC5777C MPU potentially increasing inter-core timing interferences?

Hello,

I would like to know if using of the MPU in the MPC5777C may increase memory access times. Specifically, I would like to know if there is any contention on MPU when both cores perform simultaneous accesses that pass through the MPU (e.g. CPU0 making a PRAMC_0 access simultaneously with an EBI access by CPU1 - both would pass through MPU_0).

Thanks,

Ricardo

Re: MPC5777C MPU potentially increasing inter-core timing interferences?

Hello,

The MPU does not introduce any additional contention or latency between the two cores. The MPU evaluates accesses on each of its slave ports independently and in parallel using combinational logic — there is no shared resource or serialization inside the MPU module between its slave ports.

In your specific example (CPU0 accessing PRAMC_0 via MPU_0 slave port 1, and CPU1 accessing EBI via MPU_0 slave port 0), both slave ports are served simultaneously with no interference from the MPU side.

The actual source of inter-core timing interference is the XBAR (crossbar switch), which arbitrates access when two masters target the same XBAR slave port at the same time. Since PRAMC_0 and EBI are different XBAR slave ports (port 2 and port 1 respectively), your example scenario causes no contention at the XBAR level either.

Best regards,

Peter

Re: MPC5777C MPU potentially increasing inter-core timing interferences?

Hope the document below may help. BTW, why do you want to know the timing content? Any application related?

AN12080: The Clock Monitor Unit (CMU) – Application Note

AN12176: MPC5777C Clock Calculator Guide – Application Note