Hi NXP,
Could you please confirm whether a default fail-safe reaction (assertion of FSXB and RSTB) is configured for the following faults in the respective registers?
Since the faults in the above registers are configured to provide an INTB indication, clarification is required on whether they also have any default fail-safe reaction, such as assertion of FSXB and/or RSTB.
Thanks,
Sivahari G
Hi RafaR,
I couldn't identify exactly which PN you were referring to?
I am using MFS2613AMDA6.
A fail-safe reaction such as FS0B (FSXB) and/or RSTB assertion is not automatically associated with the flag itself and depends on the corresponding fail-safe configuration.
Yes, absolutely for all regulators UV/OV fault has failsafe configuration registers "FS_I_OVUV_SAFE_REACTION1" and " FS_I_OVUV_SAFE_REACTION2 ". But Is there any provision to configure fail-safe reaction for all regulator Over Current Faults? since we have provisions to configure INTB masking/unmasking for those faults.
Example OC Faults(VBSTOV_I, VBSTOC_I, VPREOC_I, TRK1OC_I, COREOC_I)
Thanks,
Sivahari G
Hello Sivahari
Good day!
I couldn't identify exactly which PN you were referring to, but in general this applies to all versions of FS26.
RafaR_0-1787266460038.pngRafaR_0-1787266460038.pngRafaR_0-1787266460038.png
In summary, the flags in M_TSD_FLG, M_REG_FLG, and M_VSUP_FLG are interrupt sources by default. A fail-safe reaction such as FS0B (FSXB) and/or RSTB assertion is not automatically associated with the flag itself and depends on the corresponding fail-safe configuration, with TSD faults being an explicit example that can be configured to escalate into Deep Fail Safe.
I hope this information has helped you, please let me know if you need help with anything else.
Have a great day and best of luck.
Hello Sivahari
Good day!
Unfortunately, the FS26 does not have an equivalent to FS_I_OVUV_SAFE_REACTION1/2 for currents, but, all LDOs and TRKs have a current limiter, so they should remain safe even if an overclock is detected, giving you time to check it. Depending on where it originates, a different process may begin, for example, VPRE.
RafaR_0-1787355219229.pngRafaR_0-1787355219229.png
I hope this information has helped you, please let me know if you need help with anything else.
Have a great day and best of luck.