Background: The i.MX95 introduces a system manager firmware, which is responsible for power, clock, resource isolation, security management, and system-level control between kernels, essentially acting as the "backend manager" for the entire SoC. Switching between different driver modes is necessary to change the VDD_SOC voltage of the i.MX 95. But, Unlike the i.MX 93, the i.MX 95 does not support DVFS and the i.MX 95 has only one fixed DDR frequency point., it is not possible to switch between OD, ND, and LD modes under userspace.
This article will explain how to switch from OD to ND mode.
1. Test environment
HW: i.MX95 EVK board
SW: imx-oei, imx-sm
2. Voltage and frequency of i.MX 95 series processors in different modes
The voltage VDD_SOC varies in different modes.
3. Code change(Switching to ND mode as an example)
3.1. imx-sm
https://github.com/nxp-imx/imx-sm/blob/master/boards/mcimx95evk/sm/brd_sm.c#L107
index 077fa06..023a580 100755
--- a/boards/mcimx95evk/sm/brd_sm.c
+++ b/boards/mcimx95evk/sm/brd_sm.c
@@ -104,7 +104,7 @@
BRD_SM_REC_VLD_MASK)
/* Performance parameters */
-#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_ODV /* Target perf level */
+#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_NOM /* Target perf level */
#if BOARD_VOLT_SOC >= ES_ODV_UV_VDD_SOC
#define BOARD_BOOT_LEVEL DEV_SM_PERF_LVL_ODV /* Boot perf overdrive */
#elif BOARD_VOLT_SOC >= ES_NOM_UV_VDD_SOC
diff --git a/configs/mx95evk.cfg b/configs/mx95evk.cfg
index 8ac5392..5f19d42 100755
--- a/configs/mx95evk.cfg
+++ b/configs/mx95evk.cfg
@@ -459,7 +459,7 @@ PD_A55C2 stop=5
PD_A55C3 stop=4
PD_A55C4 stop=3
PD_A55C5 stop=2
-PERF_A55 start=3|3
+PERF_A55 start=3|2
CPU_A55C0 start=4
CPU_A55P stop=1
@@ -473,7 +473,7 @@ PD_A55C2 msel=1, stop=5
PD_A55C3 msel=1, stop=4
PD_A55C4 msel=1, stop=3
PD_A55C5 msel=1, stop=2
-PERF_A55 msel=1, start=3|3
+PERF_A55 msel=1, start=3|2
CPU_A55C0 msel=1, start=4
CPU_A55P msel=1, stop=1
@@ -487,7 +487,7 @@ PD_A55C2 msel=2, stop=5
PD_A55C3 msel=2, stop=4
PD_A55C4 msel=2, stop=3
PD_A55C5 msel=2, stop=2
-PERF_A55 msel=2, start=3|3
+PERF_A55 msel=2, start=3|2
CPU_A55C0 msel=2, start=4
CPU_A55P msel=2, stop=1
diff --git a/configs/mx95evk/config_lmm.h b/configs/mx95evk/config_lmm.h
index 3e3f508..999a4a1 100755
--- a/configs/mx95evk/config_lmm.h
+++ b/configs/mx95evk/config_lmm.h
@@ -152,11 +152,11 @@
{.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PD, .rsrc=DEV_SM_PD_A55P}, \
{.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PD, .rsrc=DEV_SM_PD_A55P}, \
{.lmId = 2U, .mSel = 0U, .ss = LMM_SS_PERF, .rsrc=DEV_SM_PERF_A55, \
- .numArg = 1, .arg[0] = 3U, }, \
+ .numArg = 1, .arg[0] = 2U, }, \
{.lmId = 2U, .mSel = 1U, .ss = LMM_SS_PERF, .rsrc=DEV_SM_PERF_A55, \
- .numArg = 1, .arg[0] = 3U, }, \
+ .numArg = 1, .arg[0] = 2U, }, \
{.lmId = 2U, .mSel = 2U, .ss = LMM_SS_PERF, .rsrc=DEV_SM_PERF_A55, \
- .numArg = 1, .arg[0] = 3U, }, \
+ .numArg = 1, .arg[0] = 2U, }, \
{.lmId = 2U, .mSel = 0U, .ss = LMM_SS_CPU, .rsrc=DEV_SM_CPU_A55C0}, \
{.lmId = 2U, .mSel = 1U, .ss = LMM_SS_CPU, .rsrc=DEV_SM_CPU_A55C0}, \
{.lmId = 2U, .mSel = 2U, .ss = LMM_SS_CPU, .rsrc=DEV_SM_CPU_A55C0},
3.2. imx-oei
Add the timing.c file for different DRAM frequencies under different modes to the following file, and then recompile imx-oei:
https://github.com/nxp-imx/imx-oei/tree/master/boards/mx952lp5-19/ddr
4. Boot log: The boot log shows that the CPU frequency had dropped to 1404MHz at this point.
Note: Ensure that you are using the DRAM timing.c file corresponding to the specified mode and that the compilation is error-free. To guarantee a complete error-free compilation, it is recommended to create a new timing.c file in the directory corresponding to imx-oei, complete the configuration in the Makefile, and then compile. Do not completely overwrite the contents of the current timing.c file.
For instructions on how to use Config Tool and how to update the timing.c file, please refer to the Config Tool User Guide.