2405980_en-US

[#1]

Impact of i.MX6ULL REFTOP_VBGADJ on Internal PLL and Clock Output

Hi all, / Dear Community,
We are using i.MX6ULL in our product and would like to clarify the behavior of REFTOP_VBGADJ.

Issue & Solution:
We previously experienced a USB device recognition failure on our board. Changing REFTOP_VBGADJ on CCM_ANALOG_MISC0n register from the default value (0b000) to 0b110 successfully resolved the issue.

Question:
Our customer asked whether modifying REFTOP_VBGADJ has any side effects on the i.MX6ULL's internal PLL or clock output.
Could someone please clarify whether this setting affects the PLL/clock circuitry? If it does, what specific impacts or changes in analog behavior should we expect?
Any insights or documentation references would be greatly appreciated.
Thanks in advance,

Re: Impact of i.MX6ULL REFTOP_VBGADJ on Internal PLL and Clock Output

Hi @Ichitaro_K 

On the i.MX6ULL, the LDO 1.2V bandgap voltage is 30 mV higher. Therefore, the REFTOP_VBGADJ (CCM_ANALOG_MISC0n register) bit needs to be set to 2b'110 for adjustment. And It has no impact on PLL.

B.R