We are observing an issue with the S32K358 dual-core application (Core 0 and Core 2) during power-on reset.
- When the Core 0 and Core 2 application code is flashed directly, the application executes successfully, and all functionalities operate as expected.
- However, after performing a Power-On Reset (POR), control comes to Core 0 but fail to execute the application as expected and core 2 not even executed.
- The issue is consistently reproducible following a POR when the application is started directly without the bootloader.
- In contrast, when the application is launched through the bootloader, both Core 0 and Core 2 continue to execute correctly, including after subsequent PORs.
- The issue is therefore specific to the direct application startup after POR and is not observed when the application is entered through the bootloader.
Hello @Julián_AragónM,
Currently i am working with s32k358 custom board, After POR control is coming to core0 but it got stuck. This is happening when we flash application directly.
Enabling the core 2 from core 0.
Are both CM7_0_VTOR_ADDR & CM7_2_VTOR_ADDR correctly configured when flashing directly? - Yes, because first time flashing the application both core works but the issue is only after POR.
I compared with your reference project only difference i can see in system.c file
/* Size: import information from linker symbol, Type: Normal, Inner Cache Policy: Inner write-back, write and read allocate, Outer Cache Policy: Outer write-back, write and read allocate, Shareable: No, Privileged Access:RW, Unprivileged Access:RW */
#if (defined(S32K396) || defined(S32K394)) && defined(MULTIPLE_IMAGE)
rasr[6]=((uint32)0x030B0001UL)|(((uint32)__RAM_CACHEABLE_SIZE - 1) << 1);
#else
/* Disable subregion 7 & 8*/
rasr[6]=((uint32)0x030B0001UL)|(((uint32)__RAM_CACHEABLE_SIZE - 1) << 1)|(1<<15)|(1<<14);
#endif
Hello @Indhumathi,
Is this S32K358 NXP EVB, or is this a custom design?
Could you share a bit more information regarding this issue? What does "fail to execute the application as expected" mean? Is the MCU resetting, or maybe stuck in SW somewhere?
Are both CM7_0_VTOR_ADDR & CM7_2_VTOR_ADDR correctly configured when flashing directly?
Are you enabling CM7_2 through startup IVT marker (CM7_2_ENABLE = 1) or through SW (Mcu/Power driver)?
There is a simple multicore project, which starts core 2 from core 0, maybe you can use it as reference and inspect/compare configuration? S32K358 Multicore Start CM7_2 from CM7_0.
Best regards,
Julián
Hello @Julián_AragónM,
Core 0 is working even after POR, but it's not jumping to core 2.
Could you please support us to fix the issue.
Hello @Indhumathi,
The section from system.c you've shared is not relevant for S32K358, but for S32K396, I assume you meant to share S32K358's MPU configuration instead.
Core 0 is working even after POR, but it's not jumping to core 2.
Can you check project's preprocessor symbols? multi-core projects require MULTIPLE_CORE macro defined. If not a single ELF project, MULTIPLE_IMAGE macro is also required; If single-ELF it is not necessary.
If MULTIPLE_IMAGE is not set, project runs fine with a debugger attached but enters Hardfault without the debugger. This is because the startup code will not perform ECC initialization on Core 2's RAM:
I assume you are using Mcu/Power driver to enable Core 2. Are you using HLD(MCAL) or LLD(IP)?
If you try to attach a debugger to Core 2, are you able to see if core is stuck at initialization, or is the debugger unable to connect?
Lastly, are you able to provide a simple test project or configuration files + routine, where the issue is reproducible?
Best regards,
Julián