Hello NXP Team,
We are developing a custom i.MX95-based design.
In our design, PCIE1 REFCLK is sourced from the i.MX95 PCIe clock output, while PCIE2 REFCLK is sourced from an external clock generator.
Given that PCIE1 and PCIE2 use different REFCLK sources, can they still be combined to form a PCIe x2 link?
A simplified schematic snippet is attached for reference. PCIE1 REFCLK and PCIE2 REFCLK are generated from different sources in our custom design.
(PCIE1_REF_PAD_CLK are 10K terminated, PCIE2_REF_PAD_CLK_P are sourced from clock generator(U22))
Screenshot 2026-08-17 110108.pngScreenshot 2026-08-17 110108.png@Louisliyuan
No — PCIE1 and PCIE2 on i.MX95 cannot be combined into one PCIe x2 link. The i.MX95 PCIe subsystem has two PCIe Gen 3.0 interfaces, each supporting x1 lane , with two single-lane SerDes controllers and two single-lane PHYs.
That means PCIE1 and PCIE2 are independent x1 PCIe links, not two lanes of one x2 controller.
so, for your custom design:
- PCIE1 can operate as an x1 link using the i.MX95 PCIe clock output/reference-clock architecture.
- PCIE2 can operate as an independent x1 link using the external clock generator, subject to the documented separate-reference-clock requirements such as the clock-generator difference limit of 300 ppm .
- PCIE1 + PCIE2 cannot be combined into a single x2 PCIe link on i.MX95