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[#1]

RT1176 of SEMC

The clock pin level of the chip (external DRAM) is not working properly. After successfully programming the chip, it was found that the clock pin level did not change.

Core and MemoryDevelopment BoardRe: RT1176 of SEMC

Hi @qxy111 ,

Thank you for your interest in NXP's RT series products. We are happy to assist you.

The SEMC external pin of the RT1176 is powered by the NVCC_EMC I/O power domain. Therefore, the output level of SEMC_CLK is determined by the supply voltage of NVCC_EMC. Normally, its high level should match the NVCC_EMC voltage used in the design, such as 1.8 V or 3.3 V, rather than the 1.1 V core voltage.

Please first confirm the following hardware and software configurations:

1. Check if your custom development board powers on normally, especially whether the NVCC_EMC1 / NVCC_EMC2 power supplies are functioning correctly.
2: Does the VDD voltage of the external SDRAM match the NVCC_EMC voltage of the RT1176?
3: Have the SEMC-related pin muxes and SEMC clock been correctly initialized?
4: Do the SDRAM initialization parameters match the actual SDRAM device being used?
Additionally, SEMC_CLK is a high-speed clock signal. It is recommended to use an oscilloscope to measure it near the chip pins, and it is not recommended to use a multimeter to determine whether this signal is normal.

We also recommend that you refer to the MIMXRT1170-EVKB development board design. The SDRAM interface on this board has been verified and can be used for comparison and verification of schematics and software configurations.

Best Regards

May

Re: RT1176 of SEMC

The core 1.1V signal cannot be raised to the NVCC_EMC voltage.

Re: RT1176 of SEMCThe core 1.1V signal cannot be raised to the NVCC_EMC voltage.