2405580_en-US

Yes

i.MX93 MIPI CSI-2: clock lane never enters HS at 200 Mbps (data lanes OK)

Board: FRDM-i.MX93 (imx93-11x11-lpddr4x-frdm)
BSP: Linux 6.18.2, driver phy-fsl-imx9-dphy-rx.c (fsl,imx93-dphy-rx)
Camera: custom 2-lane sensor behind MAX96717 / MAX96714 GMSL2 serdes
Data rate: 200 Mbps per lane, 2 lanes, continuous clock (fixed by the
camera, cannot be changed)

PROBLEM
The clock lane never enters high speed. No frames are captured.
DPHY_RX_STATUS (0x4ae00000 + 0x48) stays at CLK_LANE_HS = 0.

WHAT WORKS
- GMSL2 link is locked. The deserializer reports VID_LOCK=1, PKT_DET=1,
and its CSI-2 output is enabled.
- We have scoped the clock lane at the SoC pins. The clock lane is
driven, makes the LP-11 to HS transition, and runs continuously
while streaming.
- Both data lanes are alive and the i.MX93 is decoding them. Polling
DPHY_STOPSTATE (offset 0x4c) in a tight kernel loop shows about 500
transitions per 15 ms on each data lane. That matches the per-line
data bursts from the camera, so the D-PHY low-power receivers are
working and are following the HS entry requests.
- The media pipeline is configured and STREAMON is accepted.

WHAT DOES NOT WORK
- CLK_LANE_HS never becomes 1. We checked it 20000 times in a tight
kernel loop, so even a very short pulse would have been seen.
- No errors are reported anywhere. INT_ST_MAIN (0x0c),
INT_ST_DPHY_FATAL (0xe0) and INT_ST_DPHY (0x110) all read
0x00000000.
- 0 bytes are captured.

REGISTER VALUES READ ON THE RUNNING BOARD
- hsfreqrange = 0x03 (the 205 Mbps row, correct for 200 Mbps)
- cfgclkfreqrange = 28 (the config clock is 24 MHz, so (24-17)*4 = 28)
- DPHY_STOPSTATE = 0x00000003 when idle, both data lanes in stop state

WHAT WE NOTICED IN THE DRIVER
The i.MX93 Reference Manual (Rev 7, section 55.3.1) says the D-PHY
start-up needs hsfreqrange, cfgclkfreqrange AND osc_freq_target[11:0]
to be configured. It also gives a value for counter_for_des_en_config_if
in Table 541.

The i.MX93 config function in phy-fsl-imx9-dphy-rx.c
(imx93_dphy_config) writes only hsfreqrange and cfgclkfreqrange. It
does not write osc_freq_target or counter_for_des_en_config_if.

QUESTIONS
1. On i.MX93, does osc_freq_target need to be programmed? If so, how
should it be written?
2. If it does not, what is supposed to make the clock lane enter HS?
3. Is 200 Mbps with a continuous clock a supported configuration on the
i.MX93 CSI-2 port?

Thank you.