Is it possible to drive RTC_XTALI with external clock with dc level of 1.8V?
since ensuring that external clock match VDD_SNVS_ANA will increase the design complexity. Also 1.8V is below the absolute maximum rating of clock inputs.
Hi @Marwan,
As stated in the Hardware Development Guide for the MIMXRT1160/1170 Processor, if you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must remain unconnected or be driven by a complementary signal. The logic level of this forcing clock must not exceed the VDD_SNVS_DIG level.
Additionally, the i.MX RT1170 Crossover Processors Data Sheet states that VDD_SNVS_DIG has an operating voltage range of 0.81 V to 0.95 V, with a typical value of 0.85 V.
This means that a 1.8 V signal would exceed the VDD_SNVS_DIG voltage level.
Best Regard,
Pablo
Hi @Pablo_Ramos
There is discrepency in the documents, as mention in other posts.
The datasheet state that it is referenced to VDD_SNVS_ANA.
Kind Regards,
Marwan
Hi @Marwan,
I apologize for the inconvenience.
Your observation is correct, and I will remark this internally.
For now, please refer to the datasheet and ensure that the external clock into RTC_XTALI does not exceed the VDD_SNVS_ANA supply level.
In this case, an external clock with dc level of 1.8V oscillator may be used, as long as VDD_SNVS_ANA is guaranteed to be at or above 1.8 V in the design.
Best Regards,
Pablo
Hi @Pablo_Ramos,
thanks for your reply,
1 - is there away to guarantee that?
since this power rail is internally generated and there is no mention about whether is it programmable or not.
2 - is there a VDD_SNVS_ANA variance between IC batches?
Kind regards,
Marwan
Hi
The i.MX RT1170 reference manual documents a software-writable trim for LDO_SNVS_DIG, but no software-accessible voltage trim for LDO_SNVS_ANA.
The datasheet specifies VDD_SNVS_ANA as 1.65 V minimum, 1.75 V typical, and 1.95 V maximum. It does not specify how that output voltage is distributed across individual chips or production batches.
Best Regards,
Pablo