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2404913_en-US

MIPI-DSI on an iMX95 no clock output
Software summary
------------------------------------------------------------
Bootloader:               U-Boot
Kernel version:           6.6.138-7.6.1-devel #1 SMP PREEMPT Fri May  8 12:46:27 UTC 2026
Kernel command line:      root=PARTUUID=74fae1d2-02 ro rootwait console=tty1 console=ttyLP0,115200
Distro name:              NAME="TDX Wayland with XWayland Upstream"
Distro version:           VERSION_ID=7.6.1-devel-20260728203137-build.0
Distro variant:           -
Hostname:                 bmr-verdin-imx95-08828817
------------------------------------------------------------

Hardware info
------------------------------------------------------------
HW model:                 Toradex Verdin iMX95 WB on Verdin Development Board
Toradex version:          0089 V1.0C
Serial number:            08828817
Processor arch:           aarch64
------------------------------------------------------------

We have a custom carrier board with the Toradex Verdin iMX95. We are running the Toradex multimedia image with customizations (the base device tree is imx95-verdin-wifi-dev.dts).

We have a custom display from YES Optoelectronics (7” 1024x600) that is a MIPI-DSI 4 lane interface. I used the device tree and driver model from the raydium rm67191 as the starting point. I am able to get the power supply timing correct on startup and the backlight comes on and the BIST works (there is a pin on the display that can be pulled high for BIST), so I believe the display is working.

All four data lanes show single-ended activity but the CLK lines are at 0 volts. At power up the CLK lines start at around 200mV and then they go to 1.2 volts for a little bit but then they go to 0 volts and they stay at 0 volts.

I know the verdin SoM works because I can get the RVT70HSDNWCA0 display to work on a Mallow carrier board.

The driver goes through probe → add panel → get modes → prepare → enable.

Am I forgetting to turn on or configure a clock somewhere maybe?

What does it mean when the CLK signals (both P and N) are at 0 volts?

My overlay looks like

/dts-v1/;
/plugin/;

&mipi_dsi {
    
    status = "okay";
    panel@0 {
        compatible = "yes,ytc700tlbd";
        reg = <0>;
        reset-gpios = <&gpio2 17 1>;//GPIO_ACTIVE_HIGH>;

        power-supply = <&reg_vcc_disp_dvdd>;

        backlight = <&lvds_backlight>;

        dsi-lanes = <4>;

        port@0 {
            reg = <0>;
            panel1_in: endpoint {
                remote-endpoint = <&mipi1_panel_out>;
            };
        };
    };

    ports {
              /delete-node/ port@1;

              port@1 {
                      reg = <1>;
                      mipi1_panel_out: endpoint {
                              remote-endpoint = <&panel1_in>;
                      };
              };
    };
};

&displaymix_irqsteer {
    status = "okay";
};

&dpu {
  assigned-clocks = <&scmi_clk 80>, //IMX95_CLK_DISP1PIX>,
                          <&scmi_clk 18>, //IMX95_CLK_VIDEOPLL1_VCO>,
                          <&scmi_clk 19>; //IMX95_CLK_VIDEOPLL1>;
        assigned-clock-parents = <&scmi_clk 19>; //IMX95_CLK_VIDEOPLL1>;
        assigned-clock-rates = <0>, <3360000000>, <420000000>;
    status = "okay";
};

&pixel_interleaver {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";

    channel@0 {
        reg = <0>;
        status = "okay";
    };
};

&display_pixel_link {
    status = "okay";
};

Can someone confirm they were able to get a MIPI-DSI display to work with the iMX95?

Any help would be appreciated! 

Graphics & DisplayLinuxMultimediaRe: MIPI-DSI on an iMX95 no clock output

Also, here is what my clock summary looks like.

cat /sys/kernel/debug/clk/clk_summary | grep -iE "mipi|dsi|dpu|display"
ldbpll_vco                          0       0        0        4800000000  0          0     50000      Y   4b400000.display-controller     ldb_vco
ldb_pll_div7                  0       0        0        342857142   0          0     50000      Y         4b400000.display-controller     ldb                  
mipiphypllbypas               0       0        0        420000000   0          0     50000      Y         deviceless                      no_connection_id     
disp1pix                      1       1        0        46666666    0          0     50000      Y         4b400000.display-controller     pix                  
dispapb                    4       5        0        133333333   0          0     50000      Y            4b400000.display-controller     apb               
camapb                     3       6        0        133333333   0          0     50000      Y            4acf0000.dsi                    pclk              
dispocram                  1       1        0        400000000   0          0     50000      Y            4b400000.display-controller     ocram             
dispaxi                    1       1        0        800000000   0          0     50000      Y            4b400000.display-controller     axi               
mipitestbyte                     0       0        0        24000000    0          0     50000      Y      deviceless                      no_connection_id        
mipiphypllref                    1       1        0        24000000    0          0     50000      Y      4acf0000.dsi                    ref                     
mipiphycfg                       1       1        0        24000000    0          0     50000      Y      4acf0000.dsi                    cfg
Re: MIPI-DSI on an iMX95 no clock output

The target pixel clock is 51.2MHz.

Re: MIPI-DSI on an iMX95 no clock output

Hi @dastotz 

Please share the screen's pixel clock.

Best Regards,
Zhiming

Re: MIPI-DSI on an iMX95 no clock output

Here is my updated clock summary.

cat /sys/kernel/debug/clk/clk_summary | grep -iE "mipi|dsi|dpu|display|video"
 ldbpll_vco                          0       0        0        4800000000  0          0     50000      Y   4b400000.display-controller     ldb_vco
       ldb_pll_div7                  0       0        0        342857142   0          0     50000      Y         4b400000.display-controller     ldb                    
 videopll1_vco                       1       1        0        2520000000  0          0     50000      Y   deviceless                      no_connection_id
    videopll1                        1       1        0        252000000   0          0     50000      Y      deviceless                      no_connection_id
       disp1pix                      1       1        0        50400000    0          0     50000      Y         4b400000.display-controller     pix                    
                                                                                                                 4acf0000.dsi                    pix                    
       mipiphypllbypas               0       0        0        252000000   0          0     50000      Y         deviceless                      no_connection_id       
          dispapb                    4       5        0        133333333   0          0     50000      Y            4b400000.display-controller     apb                 
          camapb                     3       6        0        133333333   0          0     50000      Y            4acf0000.dsi                    pclk                
          dispocram                  1       1        0        400000000   0          0     50000      Y            4b400000.display-controller     ocram               
          dispaxi                    1       1        0        800000000   0          0     50000      Y            4b400000.display-controller     axi                 
    mipitestbyte                     0       0        0        24000000    0          0     50000      Y      deviceless                      no_connection_id
    mipiphypllref                    1       1        0        24000000    0          0     50000      Y      4acf0000.dsi                    ref
    mipiphycfg                       1       1        0        24000000    0          0     50000      Y      4acf0000.dsi                    cfg
Re: MIPI-DSI on an iMX95 no clock output

There is still no high speed video data.  The CLK signals stay at 0 volts and the DATA signals are single ended (no differential output).

Does a display need to respond to a LPM command for the MIPI-DSI interface to switch to high speed mode?

Re: MIPI-DSI on an iMX95 no clock output

Hi @dastotz 

For a 51.2 MHz pixel clock, the PLL VCO should be 1792 MHz, and the PLL OUT should be 256 MHz. You can try to update the device tree and then check the logs to see if the PLL VCO, PLL OUT, and pixel clock are correct.


Best Regards,
Zhiming

Re: MIPI-DSI on an iMX95 no clock output

You are absolutely right; this was the problem!  I chose one of those clock rates just to see if my oscilloscope would show a clock and now it does!  I will update this post with the final settings and accept this as the solution once I get a clock rate closer to my desired rate.  Thank you so much for the help!

Re: MIPI-DSI on an iMX95 no clock output

Hi @dastotz 

Please try to use this configuration to get 51.2MHz pixel clock.

&dpu {
	assigned-clocks = <&scmi_clk IMX95_CLK_DISP1PIX>,
			  <&scmi_clk IMX95_CLK_VIDEOPLL1_VCO>,
			  <&scmi_clk IMX95_CLK_VIDEOPLL1>;
	assigned-clock-parents = <&scmi_clk IMX95_CLK_VIDEOPLL1>;
	assigned-clock-rates = <0>, <3276800000>, <409600000>;
};
root@imx95evk:~# cat /sys/kernel/debug/clk/clk_summary | grep -iE "mipi|dsi|dpu|display|video"
 ldbpll_vco                          0       0        0        4800000000  0          0     50000      Y   4b400000.display-controller     ldb_vco
       ldb_pll_div7                  0       0        0        342857142   0          0     50000      Y         4b400000.display-controller     ldb
 videopll1_vco                       1       1        0        3276800000  0          0     50000      Y   deviceless                      no_connection_id
    videopll1                        1       1        0        409600000   0          0     50000      Y      deviceless                      no_connection_id
       disp1pix                      1       1        0        51200000    0          0     50000      Y         4b400000.display-controller     pix
                                                                                                                 4acf0000.dsi                    pix

But the NXP didn't verified the 1024x600. According to a recent commit to the NXP linux-imx repository, the modes verified by NXP are as follows:

3	static bool imx95_dsi_is_mode_clock_valid(unsigned int clock)
 	914	{
 	915	        switch (clock) {
 	916	        case 25200:   /* 640x480@60Hz (VGA) */
 	917	        case 27000:   /* [email protected], [email protected] (NTSC) */
 	918	        case 27027:   /* 480p@60Hz, 720x480@60Hz */
 	919	        case 40000:   /* 800x600@60Hz (SVGA) */
 	920	        case 54000:   /* [email protected], 720x576@100Hz */
 	921	        case 54054:   /* 480p@120Hz, 720x480@120Hz */
 	922	        case 65000:   /* 1024x768@60Hz (XGA) */
 	923	        case 74176:   /* [email protected], [email protected] */
 	924	        case 74250:   /* 720p@60Hz, 1280x720@60Hz */
 	925	        case 108000:  /* [email protected], 1280x1024@60Hz (SXGA) */
 	926	        case 108108:  /* 480p@240Hz, 720x480@240Hz */
 	927	        case 132000:  /* 1024x768@120Hz (XGA) */
 	928	        case 148352:  /* [email protected], [email protected] */
 	929	        case 148500:  /* 1080p@60Hz, 1920x1080@60Hz */
 	930	        case 297000:  /* 2160p@30Hz, 1080p@120Hz, 3840x2160@30Hz (4K) */
 	931	                return true;
 	932	        default:
 	933	                return false;
 	934	        }
 	935	}

According to the public code from here : https://github.com/nxp-imx/linux-imx/blob/lf-6.18.20-2.0.0/drivers/gpu/drm/bridge/imx/imx95-mipi-dsi...

If the clock is not verified clocks, the DSI will not generate clock. You could try to modify this line to return MODE_OK while the mode->clock = 51200.


Best Regards,
Zhiming

Re: MIPI-DSI on an iMX95 no clock output

The issue was the imx95-mipi-dsi.c driver that I was using (it was older without some of the patches).  I patched to use the driver you suggested and set the dpu to the settings you suggested and I was able to get a 51.2MHz pixel clock.  Thank you for the help!
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‎08-21-2026 02:37 AM
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