Software summary ------------------------------------------------------------ Bootloader: U-Boot Kernel version: 6.6.138-7.6.1-devel #1 SMP PREEMPT Fri May 8 12:46:27 UTC 2026 Kernel command line: root=PARTUUID=74fae1d2-02 ro rootwait console=tty1 console=ttyLP0,115200 Distro name: NAME="TDX Wayland with XWayland Upstream" Distro version: VERSION_ID=7.6.1-devel-20260728203137-build.0 Distro variant: - Hostname: bmr-verdin-imx95-08828817 ------------------------------------------------------------ Hardware info ------------------------------------------------------------ HW model: Toradex Verdin iMX95 WB on Verdin Development Board Toradex version: 0089 V1.0C Serial number: 08828817 Processor arch: aarch64 ------------------------------------------------------------
We have a custom carrier board with the Toradex Verdin iMX95. We are running the Toradex multimedia image with customizations (the base device tree is imx95-verdin-wifi-dev.dts).
We have a custom display from YES Optoelectronics (7” 1024x600) that is a MIPI-DSI 4 lane interface. I used the device tree and driver model from the raydium rm67191 as the starting point. I am able to get the power supply timing correct on startup and the backlight comes on and the BIST works (there is a pin on the display that can be pulled high for BIST), so I believe the display is working.
All four data lanes show single-ended activity but the CLK lines are at 0 volts. At power up the CLK lines start at around 200mV and then they go to 1.2 volts for a little bit but then they go to 0 volts and they stay at 0 volts.
I know the verdin SoM works because I can get the RVT70HSDNWCA0 display to work on a Mallow carrier board.
The driver goes through probe → add panel → get modes → prepare → enable.
Am I forgetting to turn on or configure a clock somewhere maybe?
What does it mean when the CLK signals (both P and N) are at 0 volts?
My overlay looks like
/dts-v1/;
/plugin/;
&mipi_dsi {
status = "okay";
panel@0 {
compatible = "yes,ytc700tlbd";
reg = <0>;
reset-gpios = <&gpio2 17 1>;//GPIO_ACTIVE_HIGH>;
power-supply = <®_vcc_disp_dvdd>;
backlight = <&lvds_backlight>;
dsi-lanes = <4>;
port@0 {
reg = <0>;
panel1_in: endpoint {
remote-endpoint = <&mipi1_panel_out>;
};
};
};
ports {
/delete-node/ port@1;
port@1 {
reg = <1>;
mipi1_panel_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
};
&displaymix_irqsteer {
status = "okay";
};
&dpu {
assigned-clocks = <&scmi_clk 80>, //IMX95_CLK_DISP1PIX>,
<&scmi_clk 18>, //IMX95_CLK_VIDEOPLL1_VCO>,
<&scmi_clk 19>; //IMX95_CLK_VIDEOPLL1>;
assigned-clock-parents = <&scmi_clk 19>; //IMX95_CLK_VIDEOPLL1>;
assigned-clock-rates = <0>, <3360000000>, <420000000>;
status = "okay";
};
&pixel_interleaver {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
channel@0 {
reg = <0>;
status = "okay";
};
};
&display_pixel_link {
status = "okay";
};Can someone confirm they were able to get a MIPI-DSI display to work with the iMX95?
Any help would be appreciated!
Also, here is what my clock summary looks like.
cat /sys/kernel/debug/clk/clk_summary | grep -iE "mipi|dsi|dpu|display"
ldbpll_vco 0 0 0 4800000000 0 0 50000 Y 4b400000.display-controller ldb_vco
ldb_pll_div7 0 0 0 342857142 0 0 50000 Y 4b400000.display-controller ldb
mipiphypllbypas 0 0 0 420000000 0 0 50000 Y deviceless no_connection_id
disp1pix 1 1 0 46666666 0 0 50000 Y 4b400000.display-controller pix
dispapb 4 5 0 133333333 0 0 50000 Y 4b400000.display-controller apb
camapb 3 6 0 133333333 0 0 50000 Y 4acf0000.dsi pclk
dispocram 1 1 0 400000000 0 0 50000 Y 4b400000.display-controller ocram
dispaxi 1 1 0 800000000 0 0 50000 Y 4b400000.display-controller axi
mipitestbyte 0 0 0 24000000 0 0 50000 Y deviceless no_connection_id
mipiphypllref 1 1 0 24000000 0 0 50000 Y 4acf0000.dsi ref
mipiphycfg 1 1 0 24000000 0 0 50000 Y 4acf0000.dsi cfgThe target pixel clock is 51.2MHz.
Hi @dastotz
Please share the screen's pixel clock.
Best Regards,
Zhiming