Hi Team,
We are working with an i.MX8MP custom board based on the i.MX8MP EVK configuration.
On the i.MX8MP EVK, we have an SPI device connected through ECSPI2. With the existing EVK Device Tree configuration, SPI communication is working correctly, and we can observe the expected SCLK waveform on the oscilloscope.
On our custom board, the SPI interface is connected to ECSPI1 instead of ECSPI2.
We therefore modified the Device Tree configuration to use ECSPI1. However, with ECSPI1, we are not able to observe the expected/correct SPI clock pulses on the SCLK pin.
We have tried several different Device Tree configurations, but the issue remains.
1. ECSPI1 configured similar to the existing ECSPI2 configuration
We changed the controller from ECSPI2 to ECSPI1 and created the corresponding ECSPI1 pinctrl group, including SCLK, MOSI, MISO and CS.
2. Separate CS pinctrl group
We also tried defining a separate pinctrl_ecspi1_cs and using it along with the ECSPI1 pinctrl group.
3. Explicit ECSPI1 pinmux configuration
We also tried explicitly defining the ECSPI1 pins.
However, with ECSPI1, we are still unable to observe the expected SPI clock pulses.
We would like to know when configuring ECSPI1 on i.MX8MP, are there any additional Device Tree or pinctrl changes required apart from enabling &ecspi1 and configuring the ECSPI1 SCLK/MOSI/MISO/CS pins?
In particular, is there any ECSPI1-specific pinctrl, clock, IOMUX, or other Device Tree configuration that needs to be added for ECSPI1 to operate correctly?
The same SPI setup works on ECSPI2, so we would like to understand whether there is any additional configuration required when moving the interface from ECSPI2 to ECSPI1. Thanks in advance for your guidance.
Hi ,
Please find the dts file attached
Hi @SWETHA1
Please share your dts file about ECSPI1.
B.R
Hi @SWETHA1
I have checked your dts file, I found the following errors：
1. ECSPI pins have been reused, causing a pin usage conflict. Please remove this part or use other pins for reuse.
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x48
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x48
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x48
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
2. The ECSPI1 chip select (CS) configuration is contradictory. Please change it to the following code.
pinctrl_ecspi1_cs: ecspi1cs {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000
>;
};
B.R
Hi @pengyong_zhang,
Please find the below observations
1. Logic analayser result when used the suggested changes
2. Another observation when used the below patch on top of the previously attached dts
the above graph observed with this changes
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80
>;
};
With the suggested changes, we could see the clock is not as expected.
Observation 1: The result obtained after applying the suggested DTS changes. However, the SPI clock waveform is still not as expected, and the overall SPI signal behavior does not match the expected result.
Observation 2: When MISO is left floating, CS shows two unwanted spikes, which is not the desired behavior. CS is initially driven low. Even when CS is configured to be driven high through the DTS, it is initially driven high as expected; however, after a transaction, CS appears to go low again.
Could you please share your insights on this and guide to proceed further