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[FRDM-IMXRT1186] Question about ADC Power Sequencing (VDDA_1P8 vs 3P3)

I am reviewing the FRDM-IMXRT1186 (SCH-95302 Rev.A4) and the RT1180 Data Sheet Rev.9.

The datasheet requires VDDA_ADC_1P8 to be powered prior to VDDA_ADC_3P3. However, on the FRDM board, VDDA_ADC_1P8 comes from an AMS1117-1.8 regulator tied to VDD_3V3, meaning it follows the 3.3V rail's soft-start.

Additionally, VDDA_ADC_3P3 is left floating by default (R337=DNP).

My questions:

1.Is the FRDM board considered compliant with the datasheet sequence given this implementation?

2.For a production design, is it mandatory to use a PMIC or an LDO with an EN pin to strictly meet the "prior-to" requirement?

3.I have attached a screenshot of the relevant schematic section. I will post my detailed analysis in the comments below to keep this initial post clear.

FRDM-Trainingi.MXRT 106xRe: [FRDM-IMXRT1186] Question about ADC Power Sequencing (VDDA_1P8 vs 3P3)

Hi @rejust ,

Thank you so much for your interest in our products and for using our community.

Yes, from the default FRDM-IMXRT1186 schematic, the design is intended to meet this sequencing requirement.

R337 is DNP by default, so VDDA_ADC_3P3 is not directly tied to VDD_3V3 through the 0 Ω bypass path. Instead, VDDA_ADC_3P3 is supplied through the U17 MOSFET sequencing circuit. This circuit is controlled by the VDDA_ADC_1P8 / ADC_1V8_IN rail, so VDDA_ADC_3P3 is enabled only after VDDA_ADC_1P8 is established.

For production design, a PMIC is not mandatory. Any reliable sequencing method is acceptable, such as a PMIC, LDO/load switch with EN control, or a MOSFET sequencing circuit, as long as the timing at the SoC pins meets the datasheet requirement.

Wish it helps you

Best Regards

May