2402745_en-US

[#1]

PCA9615

I am writing to ask for help with the circuits at either end of dI2C communication - between two PCBs across a twisted wire bundle (DSDAP & DSDAM; DSCLP &  DSCLM; two GND; and two 5V lines). Leading up to this I decided to test Gemini so I regretably relied on AI to generate the parts of the two PCBs that related to the dI2C comms. Attached are the parts of the schematics associated with the dI2C. Unsuprisingly there is no comms between the boards, but my laziness and I have to say stupidity (leason learnt) has cost me a lot of time. I finally referred to the datasheet and the user manual for the demo board and one obvious difference is that there are 600 Ohm resistors between the positive lines (DSCLP and DSDAP) and VDD(B), the same from the negative lines (DSCLM and DSDAM) and VSS, and 120 Ohms between the respective positive and negative lines which apparently result in 100 Ohms between the positive and negative lines (I know that 1/600 + 1/120 = 1/600 + 5/600 = 100, but I can't see it electrically- maybe because I'm a mechanical engineer ??). Is the error (maybe one of a number of errors) caused by not having what may be considered a 600 Ohm pull up resistor, a 600 Ohm pull down resistor and a 120 Ohm resistor between the respective pair of wries (characteristic impedance of a 28 AWG twisted wire pair is about 100 Ohms cabling used in internal data links and USB/Ethernet configurations and 78 Ω to 95 Ω for standard spacing configurations using PVC or FEP insulated wires), but instead a simplified and likely erroneous version of just a single 100 Ohm resitor at either end of the connecting wire on the dI2C side of the PCA9615? 

That is one significant difference between what AI gave me and what I see in Figs 1, 7, 8 and 9 of the datasheet. Another difference is that AI suggested different capacitor arrangements for the two PCBs whereas there's only one type of arrangement on the demo board (which I assume gets used on both sides of the dI2C connecting line). Further, there appears to be two capacitors for each of the VDDA pin and the VDDB pin - both ceramic capacitors (although my first thought was that the two yellow capacitors would have been tantalum type). Can I use the capacitor arrangement provided in the demo user manual and ignore what AI provided and shown in the attached?

Another issue is that on the master side (on which I am using a 3.3V microcontroller) originally Ai instructed that the enable pin be conencted to the 5V line, but after having had the boards made, the lack of any function across the two boards in part prompted the AI to determined that the enable pin on the master side should have been connected to the 3.3V line (VDD(A) on the master board was connected to the 3.3V line). It then requested that all all supply to the enable pin on the master PCB be cut completely as a test. Can you please advise what supply, if any all, should be channeled to the EN pin? I will not be hot swapping any electrical hardware during test or final operation.

I am considering implementing the above changes, but would really appreciate your help before I proceed further with costly boards.

Re: PCA9615

Just a further thing regarding the capacitors, only decoupling capacitors were suggested for both VDDA and VDDB pins on the master PCB. Decoupling capacitors were also suggested for the slave PCB, but two additional capacitors were also suggested for the VDDB pin on slave PCB. 

Re: PCA9615

Hello!

Thank you for the detailed explanation.

Please note that NXP provides an evaluation board for the PCA9615 family that can be used as a reference design for your implementation. We strongly recommend comparing your schematic against the PCA9615 evaluation board and its associated user manual, as the design includes the recommended differential I²C termination network, biasing resistors, decoupling capacitors, and EN pin connections that have been validated by NXP.

Using the evaluation board schematic as a baseline is often the best approach when designing a custom PCA9615-based system, as it minimizes the risk of configuration or layout issues and follows the recommendations provided in the datasheet and application documentation.

We suggest reviewing the evaluation board schematic and updating your design accordingly before committing to another PCB revision.

https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/ic-i3c-bus-repeaters-buffers-an...

Hope this helps!