Dear NXP team,
We are working on an improvement activity where we need to have the 8MHz SPI SCLK to be periodic within SPI transactions. We measured the SPI SCLK for 8MHz (which is driven by the SPI peripheral driver in S32K322) and found that 50% duty is not maintained. When we lower the frequency to 1/2/4 MHz we see 50% duty being maintained for those SCLK frequencies.
Question - Is this any Hardware limitation of the Peripheral driver or by changing the driver settings, desired 50% duty can be obtained for 8MHz?
PFA the screenshots where duty is maintained for 1MHz and not for 8MHz
Note: We have connected Logic Analyzer from Saleae that has higher sampling resolution (250MS/s) to measure the SPI signals
Hi,
the LPSPI clock duty cycle is determined by the SCKSET and SCKHLD timing parameters. A 50/50 duty cycle is only obtained when these fields are programmed to equal values. Depending on the selected LPSPI functional clock and the divider values required to generate 8 MHz, an exact 50/50 duty cycle may not be achievable due to the timing resolution of the clock generator. The observed 76 ns / 48 ns high-low times appear consistent with such divider quantization effects.
BR, Petr