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[#1]

i.MX8M Nano PTP clock accuracy

We are evaluating IEEE 1588 PTP for synchronizing multiple i.MX8M Nano systems that acquire data through the SAI interface.

Our synchronization requirement is for the sampling time across multiple units to remain within 2 µs.

On our hardware, ENET1_1588_EVENT0_OUT is routed externally back into GPT_CAPTURE1. The intended architecture is:

• Synchronize the ENET PTP Hardware Clock on each unit using hardware-timestamped PTP.
• Generate a periodic timing event using ENET1_1588_EVENT0_OUT.
• Capture that event with GPT to correlate the PTP clock to a local hardware timer.
• Use the measured relationship between the PTP timebase and the audio clock to adjust the AudioPLL on each slave unit so that its SAI sampling rate tracks the master unit.
• Maintain both sample-rate synchronization and a known phase/sample-index relationship between units.

We found the NXP presentation “i.MX IEEE 1588 1PPS Test”, which shows how to enable the FEC 1588 output and notes that the general procedure applies to the i.MX8M family. However, the presentation demonstrates signal generation only and does not provide any specification or measured result for synchronization accuracy, PPS skew, output jitter, or unit-to-unit phase error.

We have also reviewed the i.MX8M Nano datasheet and reference manual, but have not found a guaranteed timing specification for any of the following:

1. Maximum synchronization error between two i.MX8M Nano ENET PTP hardware clocks when using hardware packet timestamping.
2. Timing accuracy or jitter of ENET1_1588_EVENT0_OUT relative to the programmed ENET PTP timer compare value.
3. Unit-to-unit variation in the latency from the ENET PTP timer compare event to the external EVENT0_OUT pin.
4. Total uncertainty when ENET1_1588_EVENT0_OUT is looped back into GPT_CAPTURE1.
5. Expected practical synchronization performance using the NXP Linux BSP and ptp4l.

Could NXP provide any guidance on the following?

• Is there an undocumented characterization result or expected accuracy for the FEC PTP clock and ENET1_1588_EVENT0_OUT?
• Is the output edge generated entirely in hardware from the ENET PTP timer, with deterministic latency relative to the timer compare?
• Is the edge timing quantized only by ENET_TIMER_CLK_ROOT, or are there additional asynchronous clock-domain crossings that introduce variable latency?
• Is there a known maximum uncertainty for GPT input capture when capturing the looped-back event?
• Has NXP measured PPS-to-PPS skew between two i.MX8M devices synchronized over PTP?
• Is synchronization within 2 µs considered a reasonable expectation when using hardware timestamping and a controlled wired Ethernet network?
• Are there recommended ptp4l, FEC driver, clock-tree, or device-tree settings for obtaining the best synchronization accuracy on i.MX8M Nano?
• Is there any existing NXP example for disciplining the AudioPLL or an SAI media clock from the ENET PTP clock?

We plan to verify the implementation experimentally by placing two boards on the same PTP network and measuring the time difference between their ENET1_1588_EVENT0_OUT signals using a two-channel oscilloscope. We would then separately measure SAI frame-clock or sample-clock alignment after implementing the AudioPLL control loop.

Would this be the recommended method for characterizing the achievable PTP synchronization accuracy, or is there another internal signal, register, driver statistic, or NXP test method that would provide a better measurement?

Any timing characterization data, internal design guidance, relevant application notes, or BSP examples would be appreciated.

i.MX 8M | i.MX 8M Mini | i.MX 8M NanoRe: i.MX8M Nano PTP clock accuracy

I searched and consult it, for imx8mn, we only validate the IEEE 1588 PTP support, doesn't do any Timing accuracy or latency testing, we can help customer bring up the IEEE 1588 PTP output setup, but couldn't offer these data since we haven't tested it yet