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KW45B41Z-EVK: BLE clock source and internal clock path for the BLE radio to get 2.4GHz

Hello NXP Team,

I am working with the KW45B41Z-EVK  and would like to understand the clock architecture used by the BLE subsystem.

I have gone through the KW45B41 Reference Manual, KW45B41Z-EVK User Manual, and the SDK clock initialization code, but I could not find a detailed description of the BLE clock source and its internal clock path.

Could you please clarify the following:

1. What is the primary clock source used by the BLE (for example, SOSC, FRO, PLL, or another clock source)?
2. What is the complete clock path from the oscillator to the BLE radio to get 2.4GHz? Specifically, which clock modules, multiplexers, dividers, or PLLs are involved before the clock reaches the BLE subsystem?
3. Does the BLE subsystem use different clock sources during advertising, scanning, connected mode, or sleep mode?
4. Is there a clock tree diagram or application note that illustrates the BLE clock architecture for the KW45B41 device?
5. Which sections of the Reference Manual or any other NXP documentation describe this in detail?

If possible, a block diagram of the BLE clock path or references to the relevant documentation would be greatly appreciated.

Thank you for your support.

Best regards,

Re: KW45B41Z-EVK: BLE clock source and internal clock path for the BLE radio to get 2.4GHz

Hello,
Hope you are doing well!

The primary clock source for the BLE subsystem is the OSC-RF (RF Oscillator), in conjunction with an external crystal or resonator, generates a reference clock for the KW45 Radio. It supports either 26 MHz or 32 MHz and operates in a completely separate power domain from the main CPU clock domain, serving exclusively as the reference clock for the Radio subsystem.

The KW45 Reference Manual includes two figures that might be particularly helpful to visualize the BLE clock architecture:
Figure 68. Device clock sources and trees
Figure 222. Radio Clocking

As described in section 55.4.4 of the RM, the radio uses three clock sources: the Radio XO (OSC-RF), the FRO-192M, and the SOC 32.768 kHz from the CCM32K module. During active operating mode (including advertising, scanning, and connected), all three clock domains are simultaneously active. The OSC-RF and its XCVR PLL are running to support radio TX and RX (this is managed internally by the NBU firmware), the FRO-192M is clocking the NBU CM3 core for Link Layer execution, and the 32K_CLK is running in the background to track connection and advertising intervals.

For low-power mode behavior, Table 209 describes how each clock module behaves across the different power states.

It might also be helpful to use the Clocks Tab from MCUXpresso Config Tools. There, you can visualize the clock sources routed for each domain, see the interactive clock tree, and change clock sources as needed. It also generates the clock initialization source code, which can be a helpful reference for understanding how each clock domain is configured at startup.

Best regards,
Sofia.