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KW45B41Z-EVK: BLE clock source and internal clock path for the BLE radio to get 2.4GHz

Hello NXP Team,

I am working with the KW45B41Z-EVK  and would like to understand the clock architecture used by the BLE subsystem.

I have gone through the KW45B41 Reference Manual, KW45B41Z-EVK User Manual, and the SDK clock initialization code, but I could not find a detailed description of the BLE clock source and its internal clock path.

Could you please clarify the following:

1. What is the primary clock source used by the BLE (for example, SOSC, FRO, PLL, or another clock source)?
2. What is the complete clock path from the oscillator to the BLE radio to get 2.4GHz? Specifically, which clock modules, multiplexers, dividers, or PLLs are involved before the clock reaches the BLE subsystem?
3. Does the BLE subsystem use different clock sources during advertising, scanning, connected mode, or sleep mode?
4. Is there a clock tree diagram or application note that illustrates the BLE clock architecture for the KW45B41 device?
5. Which sections of the Reference Manual or any other NXP documentation describe this in detail?

If possible, a block diagram of the BLE clock path or references to the relevant documentation would be greatly appreciated.

Thank you for your support.

Best regards,