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2400861_en-US

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S32K3 spi clk abnormal low

I use S32K344 EVB to do spi test. I use LPSPI1 unit as master with pin from PTB14 to PTB17, and RTD 4.0.0 P19. The spi is mode 3: CPOL=1, CPHA=1

After call for Spi_SyncTransmit, I measure the scope like below, The clk pin get to low before the frame really tramsmit, what might be the reason for that? How to fix it?

zyt_0-1785493991563.png



Re: S32K3 spi clk abnormal low

Hi @zyt 

This behavior is typically caused by the first workaround for ERR050456, which performs a reset of the LPSPI module. This situation has already been discussed in other threads, such as Extra SPI Clock Pulse Appears Before CS Line Goes Low on [MCU S32K312].

As explained in that thread, an alternative workaround can be applied that is expected to eliminate the low pulse. To enable this workaround define the following macro in your project:

ERR_IPV_LPSPIV2_E050456_2ND_SOLUTION


BR, VaneB

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