The above mentioned pad control settings are not described in the reference manual. Why and how can we test / trim these settings?
Hello @NLFOHE
Hope you are doing very well.
Actually, that pad is under the register's name: IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B.
Mux mode register should be configured as uSDHC3 (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B):
Best regards,
Salas.
Hello Salas,
Issue not yet solved due holiday period. Is there any application note how to use SCC on this specific clock signal?