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For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core.

For chip S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core. Are there any implementation schemes and demos available?

Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core.

Hello, @zhijie 

Thanks for your post.

As far as I know, there seems no such similar formal demo/examples existed, you may need to develop it yourself.

For communication between M and A cores, currently IPCF is provisioned by NXP, but it is by default based on SRAM.

BR

Chenyin

Re: For S32G399, configure DDR‑based shared memory to be accessed by both A‑Core and M‑Core.

Has any developer within the NXP Community completed such an implementation? Relevant documents or experience sharing will be greatly appreciated.