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Does the S32K344's hardware QSPI support (Continuous Clock) configuration?

As the title suggests, I want to continuously output a clock so that my downstream devices can process data based on this clock.

Re: S32K344的硬件QSPI，是否支持（连续时钟/ Continuous SCK）的配置？

Hello @Zhangbohan,

Unfortunately, S32K3 SPI module does not support continuous SCK. One option is to use the "Continuous Transfer":

"In Master mode, CONT keeps the PCS asserted at the end of the frame size, until a command word is received that starts a new frame."

Another option is using a GPIO to act as CS and controlled by software.

In either way, the SPI SCK is generated when pushing data into the SPI TX buffer. If you use standard driver (MCAL or RTD), then the SCK pulse will be control by driver through pushing data to FIFO. The user can't control it.

As far as I know, only S32K9-K7-K6 devices' DSPI module support continuous SCK mode. From S32K39 Reference Manual:

Best regards,
Julián

Re: S32K344的硬件QSPI，是否支持（连续时钟/ Continuous SCK）的配置？Thank you very much for your reply. I have re-evaluated my solution and have another question. Does the S32K344 support DMA transfer via QSPI? I see relevant registers at the register level; however, there are no enable or channel configuration options in QSPI_IP; it seems configurable at the MCAL layer. This makes me unsure whether QSPI+DMA is supported, and if there are any relevant examples. The existing example "Mem_43_EXFLS" doesn't seem to use DMA.Re: S32K344的硬件QSPI，是否支持（连续时钟/ Continuous SCK）的配置？

Hello @Zhangbohan,

Yes, QSPI instance does support DMA usage, you can refer to chapter 78.5.4.1 from the S32K3XX Reference Manual for considerations. 

However, I am not aware of any QSPI_IP + DMA examples.

Best regards,
Julián