Hello NXP,
Target uC : S32K388
I am using the burst registers TCBR and TDBR0-127 for SPI transmissions using eDMA.
Current frame size is 32 bits and everything works as expected
Now for an SPI frame size which is less than 32 bits, how can the burst registers be used without changing the dma transfer size, in between.
Can TCBR be written in 16 or 8 bit units.
Can TDBRn be written in 16 or 8 bit units
If not, could you give hints as to how to setup the dma channel for frame sizes 16 and 8 bits.
Thanks in advance
Yes, both TCBR and TDBRn support 16-bit and 8-bit writes — no DMA transfer size change is needed.
TCR[FRAMESZ].[7:0] only stages the data — a second 8-bit write to [15:8] is required to trigger the push.RM reference — S32K3xx Reference Manual, Rev. 12, 2025-11-11:
Section 70.6.1.17 — Transmit Data (TDR):
"You can write to this register using 32-, 16-, or 8-bit writes. Both 8-bit and 16-bit writes of transmit data zero-extend the data written and push the data into the transmit FIFO. To zero-extend 8-bit and 16-bit writes (to 32 bits) means that the higher order (most significant) empty parts of the 8-bit and 16-bit writes are filled with zeroes."
Section 70.3.6.1 — DMA support registers (TCBR / TDBR0–TDBR127): Documents the burst alias region designed for incrementing 8-bit, 16-bit, or 32-bit DMA write accesses to the transmit FIFO.
Reg TCBR, if the 16 bit write to [15:00] or the second 8-bit write to [15:8] pushes the data into the FIFO as a command entry, how can the entire TCR be updated. Only the frame size selection is available on the lower half word. The other settings like CPOL,CPHA,PCS etc comes in the upper half word.