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[#1]

s32k344, LPSPI small clock gap between frames of a continuous sequence

- I am having a problem communicating between an NXP MCU S32K344 LPSPI module (Controller) and a Holt HI-35930 (Peripheral).

The code is writing 2 frames, each an 8 bit word. over the LPSPI to an ARINC communication device HI-35930.  I verified all settings are correct. cpol = 0, cpha = 0,  LSBF = MSB, BYSW=no, RXMSK, TXMSK =0, TCR[FRMSZ]=7.

The code uses the TRC[CONT and TRC[CONTC] bits to control the PCS. The PCS stays asserted for the entire sequence of 2 frames, see picture. The clock, likewise pulses over the 2 frames. The SOUT signal has the expected data on it, frame 1 = opcode 0x80, frame 2 - dummy data 0x00

The problem is with SIN. There is no data back. ( opcode 0x80 is to read a register where I was expecting at least one bit set high).

The RXCOUNT does increment on each frame to a max of 2.

-Using the same settings, I concatenate the same opcode and data into one 16-bit frame, set TRC[CONT and TRC[CONTC] = 0 since there is one frame TRC[FRMSZ]=15. The transmission works and SIN returns real data.

What do you think is wrong here?

Yellow - PCS signal

Pink - Clock signal

Blue - SIN to the MCU

Green - SOUT from the MCU

Re: s32k344, LPSPI small clock gap between frames of a continuous sequence

The data for MOSI and MISO is empty. Do you have right SPI bus hardware schematics design?

Re: s32k344, LPSPI small clock gap between frames of a continuous sequence

Hi @ekmas-19,

You described the transmission as sending 2 bytes — 0x80 and 0x00. However, the oscilloscope clearly shows 2 x 32-bit words separated by a small gap, not 2 x 8-bit frames. Can you clarify this?

Regarding the inter-frame gap — this is expected behaviour. CONT = 1 only keeps CS/PCS asserted between frames; it does not affect SCK. The clock behaves exactly as it would with CONT = 0.

Regards,

Daniel