I am currently using SWD to debug the LPC54113 chip. I have halted the core and then set some debug registers starting with 0xE000.
I found that when I read the internal flash of the chip, the address 0x0~0x200 always had incorrect data, resembling an interrupt vector table rather than the actual program stored in the FLASH. By reading from other addresses, the correct data can be obtained, all of which are 0xFFFFFFFF.
The chip did not program any data. Through using JLINK for reading, the address 0x0~0x200 are 0xFFFFFFFF. However, JLINK uses FLM to write to RAM for reading, I cannot know how it processes the reading of the 0x0 to 0x200 address range.
The steps I followed were:
write abort, 0x1E
write select, 0x0
write tar, 0x0
write csw, 0x23000012
and then read drw until the internal flash end address.
I want to read the physical flash contents in 0x0, What should I do?
I need to change AP bank or other operations?
Hello,
You may be reading the Cortex-M memory alias rather than the physical flash contents. On the LPC54113, address 0x00000000 is mapped to the currently active memory (flash, boot ROM, or RAM) depending on the boot configuration and remap settings. If the device is blank, the boot ROM can present a valid vector table at 0x0, which explains why you see interrupt vectors instead of 0xFFFFFFFF.
Hi,
TAR = 0x0, the returned data reflects the current system memory mapping visible to the CPU. For LPC5411x devices, the first 512 bytes at address 0x00000000 are remapped to the Boot ROM, so the data observed in this region is a valid interrupt vector table rather than the actual contents stored in Flash.TAR = 0x0 and consecutive DRW accesses. Instead, a Flash algorithm or IAP-based method that can access the raw Flash array contents should be used, like you use Jlink to read.The LPC5411X did not have the IAP sample for read physical flash.
