2397882_en-US

[#1]

How to test Sideband ECC error injection on i.MX 8QuadXPlus / i.MX 8DualXPlus?

Hello NXP team,

I am testing the DDR Sideband ECC functionality on an i.MX 8QuadXPlus / i.MX 8DualXPlus platform with a 40-bit DDR3L interface (32-bit data + 8-bit ECC).

According to AN13566, Inline ECC errors can be injected by unlocking the ECC parity region through ECC_REGION_PARITY_LOCK and modifying the ECC parity bits. However, I could not find a detailed error-injection or validation procedure for Sideband ECC.

AN13566 mentions that Sideband ECC uses an additional ECC byte and that the controller checks this byte during DDR reads. It also mentions that Sideband ECC supports an automatic scrub RMW operation after detecting a correctable single-bit error.

Could you please clarify the recommended method to test Sideband ECC?

1. Is there a hardware error-injection or data-poisoning register for Sideband ECC?
2. How can software inject a single-bit correctable error?
3. How can software inject a double-bit uncorrectable error?
4. Which ECC status registers and interrupt signals should be checked?
5. How can we verify that the Sideband ECC scrub operation has corrected and written back the data?
6. Is there any example code, test procedure, or DDR controller register sequence available?

Our configuration is:

• SoC: i.MX 8QuadXPlus / i.MX 8DualXPlus
• DDR type: DDR3L
• DDR interface: 40-bit, 32-bit data + 8-bit ECC

Thanks.