i work with iMX RT1011 Nano Kit
nice board
i try to setup edma flexio for 8bit parallel from shifter 0
timer 0 set to 30mhz edma sent 512bytes (one per request )
code:
FLEXIO_DEV->SHIFTCTL[TX_SHIFTER] =
FLEXIO_SHIFTCTL_TIMSEL(WR_TIMER)
| FLEXIO_SHIFTCTL_TIMPOL(0U)
| FLEXIO_SHIFTCTL_PINCFG(3U) /* output */
| FLEXIO_SHIFTCTL_PINSEL(DATA_PIN_START)
| FLEXIO_SHIFTCTL_PINPOL(0U)
| FLEXIO_SHIFTCTL_SMOD(2U); /* transmit */
/* Timer0: WR strobe, one pulse per byte
* TIMCMP low byte = (flexio_clk / (2*wr_clk)) - 1
* TIMCMP[15:8] = (beats*2)-1 = 1 for one byte per shifter load */
timDiv = (flexioClk_Hz / (2U * wrClock_Hz));
if (timDiv != 0U) { timDiv -= 1U; }
timDiv &= 0xFFU;
FLEXIO_DEV->TIMCMP[WR_TIMER] = (1U << 8U) | timDiv;
FLEXIO_DEV->TIMCFG[WR_TIMER] =
FLEXIO_TIMCFG_TIMOUT(1U)
| FLEXIO_TIMCFG_TIMDEC(0U)
| FLEXIO_TIMCFG_TIMRST(0U)
| FLEXIO_TIMCFG_TIMDIS(2U) /* disable on compare */
| FLEXIO_TIMCFG_TIMENA(2U) /* enable on trigger high */
| FLEXIO_TIMCFG_TSTOP(0U)
| FLEXIO_TIMCFG_TSTART(0U);
FLEXIO_DEV->TIMCTL[WR_TIMER] =
FLEXIO_TIMCTL_TRGSEL((4U * TX_SHIFTER) + 1U) /* Shifter0 flag */
| FLEXIO_TIMCTL_TRGPOL(1U) /* active low */
| FLEXIO_TIMCTL_TRGSRC(1U) /* internal */
| FLEXIO_TIMCTL_PINCFG(3U) /* output */
| FLEXIO_TIMCTL_PINSEL(WR_PIN)
| FLEXIO_TIMCTL_PINPOL(1U) /* WR active low */
| FLEXIO_TIMCTL_TIMOD(1U); /* dual 8-bit baud/bit */
/* Enable DMA request from Shifter0 */
FLEXIO_DEV->SHIFTSDEN |= (1U << TX_SHIFTER);
/* Enable FlexIO */
FLEXIO_DEV->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
i saw the signal on the logic analyzer
look like what i am except but i get missing data in some 512 pack
i mean send for example 200bytes and stop after that send ok all the 512
tzahi
Hi @TZAHI ,
Thank you so much for your interest in our products and for using our community.
The most likely direction to check is whether the eDMA can continuously refill the FlexIO SHIFTBUF fast enough at the 30 MHz WR clock.
With the current one-byte-per-request style configuration, the DMA request rate may be very high. This can be tight for eDMA, bus arbitration, and the FlexIO SHIFTBUF refill timing.
A likely symptom is TX shifter underrun. Please first check SHIFTERR immediately after the failed transfer, before reinitializing or clearing FlexIO:
Please also try increasing the CPU/bus clock if possible, or reducing the WR clock below 30 MHz, for example to 20 MHz or 10 MHz. If the transfer becomes stable at a lower WR clock, it would strongly indicate that the issue is related to DMA/FlexIO refill timing.
Wish it helps you
Best Regards
May