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Request for Dual-Core Ethernet Example on i.MX RT1176 (One Ethernet per Core)

Hello NXP Team,

I am currently working on the i.MX RT1176 evaluation board using MCUXpresso IDE v11.9.1 (Build 2170, 2024-04-19).

I would like to know whether NXP provides any multicore example project that demonstrates the use of both Cortex-M7 and Cortex-M4 cores with independent Ethernet interfaces.

My requirement is as follows:

• Ethernet Port 1 should be initialized and managed by the Cortex-M7 core.
• Ethernet Port 2 should be initialized and managed by the Cortex-M4 core.
• Both Ethernet interfaces should operate simultaneously and independently on their respective cores.
• If inter-core communication (such as RPMsg or MU) is required, I would appreciate any example or documentation explaining the recommended approach.

I have searched the MCUXpresso SDK examples but have not found a project matching this use case.

Could you please let me know:

1. Is there any official NXP multicore example demonstrating one Ethernet controller on the M7 core and the other Ethernet controller on the M4 core?
2. If such an example is available, could you please share the project or provide the corresponding SDK example name or repository link?
3. If no such example exists, could you suggest the recommended architecture for implementing this configuration on the i.MX RT1176?

Any reference projects, application notes, or documentation would be greatly appreciated.

Thank you for your support.

Best regards,

Aravind Togaralli

Re: Request for Dual-Core Ethernet Example on i.MX RT1176 (One Ethernet per Core)

Dear @Aravind_Togaralli ,

Unfortunately, there is currently no official example that demonstrates both the Cortex-M7 and Cortex-M4 running independent Ethernet interfaces simultaneously.

However, the recommended architecture is to keep the two Ethernet subsystems completely independent:

• Assign one Ethernet controller (e.g., ENET/ENET_QOS) to CM7 and the other to CM4.
• Each core should maintain its own MAC driver, PHY control, lwIP stack, netif instance, DMA descriptors, packet buffers, interrupts, and network configuration.
• Use RPMsg-Lite, MU, or shared memory only for inter-core control and status communication when needed.
• Consider using RDC/XRDC2 to isolate Ethernet peripherals and memory resources between the two cores during development.
• For Ethernet DMA buffers, ensure the selected memory region is accessible by both the corresponding CPU and Ethernet DMA master.

A suggested implementation approach is:

1. Start from a working RT1170 multicore example.
2. Bring up Ethernet on CM7 using a standard lwIP example.
3. Bring up Ethernet on CM4 using the second Ethernet controller.
4. Verify both Ethernet interfaces operate simultaneously without IPC.
5. Add RDC/XRDC2 isolation if required.
6. Introduce RPMsg-Lite or MU/shared-memory communication only if the application requires inter-core interaction.

You may also find application note AN13264 helpful, as it provides guidance and recommendations for RT1170 multicore application development.

Best Regards,

Shelly Zhang