2396782_en-US

Yes

Flash configuration confusion RT1176 Octal DDR

Hello NXP

I got some issues configuring the flash memory for Macronix Octal DDR mode.

I am using the PX4 code stack on a custom board based on the NXP FMU-6XRT reference design. I am using the MX25UM51245G instead of the MX25UM51345G, but the part differences are minimal.

I am trying to run it in Macronix Octal DDR mode with DQS external sampling at atleast 100MHz. Reference design is running it at 200MHz. The Boot Memory Configuration succesfully tests the memory with the desired configuration even at 166MHz.

The configuration I have tried is the following default config. The first one, "g_flash_config" succesfully boots, writes, read, etc, but is not ideal for the software. "g_flash_fast_config" fails.

I have tried reducing the frequency to 166MHZ, 133MHz, 50 MHz, and 30MHz without results in the DTR mode in the "fast_config".

I have tried using the FCB generated from the Boot Memory Configuration, but there is some struct layout differences which have made it hard to apply to the PX4 code.

I am tried different combinations of csHoldTime, csSetupTime and dataValidTime without results aswell.

I tried DQS interal in low freq DTR Octal, but it did not work either.

What could I try next?

#include 

/****************************************************************************
 * Public Data
 ****************************************************************************/

locate_data(".boot_hdr.conf")
const struct flexspi_nor_config_s g_flash_config = {
	.memConfig =
	{
#if !defined(CONFIG_BOARD_BOOTLOADER_INVALID_FCB)
		.tag                 = FLEXSPI_CFG_BLK_TAG,
#else
		.tag                 = 0xffffffffL,
#endif
		.version             = FLEXSPI_CFG_BLK_VERSION,
		.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
		.csHoldTime          = 1,
		.csSetupTime         = 1,
		.deviceModeCfgEnable = 1,
		.deviceModeType      = kDeviceConfigCmdType_Generic,
		.waitTimeCfgCommands = 1,
		.controllerMiscOption =
		(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
		.deviceType    = kFlexSpiDeviceType_SerialNOR,
		.sflashPadType = kSerialFlash_1Pad,
		.serialClkFreq = kFlexSpiSerialClk_100MHz,
		.sflashA1Size  = 64ul * 1024u * 1024u,
		.dataValidTime =
		{
			[0] = {.time_100ps = 0},
		},
		.busyOffset      = 0u,
		.busyBitPolarity = 0u,
		.lookupTable =
		{
			/* Read Dedicated 3Byte Address Read(0x03), 24bit address */
			[0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, RADDR_SDR, FLEXSPI_1PAD, 0x18),    //0x871187ee,
			[0 + 1] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0),//0xb3048b20
		},
	},
	.pageSize           = 256u,
	.sectorSize         = 4u * 1024u,
	.blockSize          = 64u * 1024u,
	.isUniformBlockSize = false,
	.ipcmdSerialClkFreq = 1,
	.serialNorType = 2,
	.reserve2[0] = 0x7008200,
};

const struct flexspi_nor_config_s g_flash_fast_config = {
	.memConfig =
	{
		.tag                 = FLEXSPI_CFG_BLK_TAG,
		.version             = FLEXSPI_CFG_BLK_VERSION,
		.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
		.csHoldTime          = 3,
		.csSetupTime         = 3,
		.deviceModeCfgEnable = 1,
		.deviceModeType      = kDeviceConfigCmdType_Spi2Xpi,
		.waitTimeCfgCommands = 1,
		.deviceModeSeq =
		{
			.seqNum   = 1,
			.seqId    = 6, /* See Lookup table for more details */
			.reserved = 0,
		},
		.deviceModeArg = 2, /* Enable OPI DDR mode */
		.controllerMiscOption =
		(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable),
		.deviceType    = kFlexSpiDeviceType_SerialNOR,
		.sflashPadType = kSerialFlash_8Pads,
		.serialClkFreq = kFlexSpiSerialClk_133MHz,
		.sflashA1Size  = 64ul * 1024u * 1024u,
		.dataValidTime =
		{
			[0] = {.time_100ps = 10},
		},
		.busyOffset      = 0u,
		.busyBitPolarity = 0u,
		.lookupTable =
		{
			/* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data
			/* Macronix manual says 20 dummy cycles @ 200Mhz, FlexSPI peripheral Operand value needs to be 2N in DDR mode hence 0x28 */
			[0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11),    //0x871187ee,
			[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x28),//0xb3288b20,
			[0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), //0xa704,

			/* Read status */
			[4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xfa),
			[4 * 2 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),
			[4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),

			/* Write enable SPI *///06h
			[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00000406,

			/* Write enable OPI SPI *///06h
			[4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9),

			/* Erase sector */
			[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE),
			[4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),

			/*Write Configuration Register 2 =01, Enable OPI DDR mode*/ //72H +32bit address + CR20x00000000 = 0x01
			[4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000472,
			[4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000400,
			[4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),//0x20010400,

			/*Page program*/
			[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED),//0x87ed8712,
			[4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04),//0xa3048b20,
		},
	},
	.pageSize           = 256u,
	.sectorSize         = 4u * 1024u,
	.blockSize          = 64u * 1024u,
	.isUniformBlockSize = false,
	.ipcmdSerialClkFreq = 1,
	.serialNorType = 2,
	.reserve2[0] = 0x7008200,
};