Hi Team,
We are facing a reset issue in the SBC section.
During initial testing, I assembled only the NXP Semiconductors MFS2633HMDB2AD SBC section and checked the reset output. The reset line was HIGH, and the IC was working properly.
After assembling the MCU and other related components, the PMIC reset line is always LOW, and all associated reset signals are being pulled LOW.
When I connect the JTAG debugger, the reset line becomes HIGH and the system enters debug mode successfully.
Additional observations:
Removed MCU reset line using a 0Ω resistor.
MCU reset line is HIGH.
PMIC reset line remains LOW.
FS26 is working correctly in debug mode.
Without JTAG connection, the PMIC reset output remains LOW.
It appears that the issue occurs only after MCU integration. The SBC section works correctly when tested independently, but after MCU connection, the PMIC reset sequence is not releasing.
Thanks.
Hi Guoweisun,
The FS26 is operating in Debug mode, and all the power outputs (LDOs and VCORE) are present and within the expected range. However, the RESET line is still not going HIGH.
Our application includes an external watchdog, so we removed it from the circuit and tested again. Even after removing the external watchdog, the RESET line remains LOW.
Could you please let us know what other conditions could prevent the RESET line from being released or what additional checks we should perform?
Thank you.
The FCCU1 and FCCU2 pins are connected with the recommended pull-up and pull-down resistors. Should we leave these connections as they are, or do you recommend isolating the FCCU pins from the MCU as well for debugging?
In the INIT phase setting as above circled.
We ḥave checked the pins FCC 1 & 2 pin are low still the reset line is not released high
Since in debug mode still RSTB pull low which is not related with WD.
Please try to disable FCCU function in INIT phase to test it again.
Hi
Please Confirm whether there is some error for WD refresh and the power rails UV/OV.
According my last reply to disable this FCCU function in the INIT phase of SBC to test again.