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[#1]

Assistance Required for VSC8254 PHY Bring-up in 1G SGMII Mode on LX2160A

Hello everyone,

We are working on a custom board based on the LX2160A Rev2 SoC, where the VSC8254 PHY is connected to the SoC through eMDIO1. We are currently facing issues while bringing up the PHY in 1G SGMII mode.

So far, we have successfully brought up the PHY in 10G XFI mode by configuring a fixed link in both the DPC file and the Linux kernel Device Tree. After booting, we execute the NXP-provided mdio_cl45_write script to program the required Clause 45 registers, following which the link comes up and operates correctly.

However, when we switch the configuration to 1G SGMII mode, we make the following changes:

Update the DPC and Linux Device Tree to use SGMII instead of XFI.
Execute the corresponding Clause 45 register initialization sequence for 1G.
Update the SERDES reference clock from 125 MHz to 100 MHz, as required for the new configuration.
Despite these changes, the PHY link does not come up.

For reference:

The VSC8254 PHY is connected to SERDES1 MAC3 and MAC4.
We are using RCW 6 for the 10G XFI configuration.
We are using RCW 4 for the 1G SGMII configuration.
Could you please let us know if there are any additional configuration changes or initialization steps required to bring up the PHY in 1G SGMII mode?

Thank you for your time and support.

@yipingwang @chenyin_h 

Re: Assistance Required for VSC8254 PHY Bring-up in 1G SGMII Mode on LX2160A

1. Please configure RCW[SRDS_PLL_REF_CLK_SEL_S1] as "00".

2. In Linux Kernel, please configure "CONFIG_VITESSE_PHY".

3. In Linux Kernel dts file arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts, please modify dpmac3 and dpmac4 configuration similar as the following.

&dpmac3 {
phy-handle = <&aquantia_phy1>;
phy-connection-type = "usxgmii";
managed = "in-band-status";
};

aquantia_phy1: ethernet-phy@4 {
/* AQR107 PHY */
compatible = "ethernet-phy-ieee802.3-c45";
interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x4>;
};

Modify to:

&dpmac3 {

        phy-handle = <&sgmii_phy1>;

        phy-connection-type = "sgmii";

        managed = "in-band-status";

};

        sgmii_phy1: ethernet-phy@xx{

                reg = <0xxx>;//specify dpmac3 related MDIO PHY address

        };

4. Please modify dtc file dpc-usxgmii.dts as the following.

       board_info {

                ports {

                        mac@3 {

                                link_type = "MAC_LINK_TYPE_PHY";

                                enet_if = "USXGMII";

                        };

                        mac@4 {

                                link_type = "MAC_LINK_TYPE_PHY";

                                enet_if = "USXGMII";

                        };

Modify to:

        board_info {

                ports {

                        mac@3 {

                                link_type = "MAC_LINK_TYPE_PHY";

                        };

                        mac@4 {

                                link_type = "MAC_LINK_TYPE_PHY";

                        };