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S32K348-GPIO EIRQ to DMA request

Dear NXP Support Team,

I.m trying now approach, where GPIO PTD6 has setting as EIRQ14 ,rising edge detection and I want to map this pin signal to the DMA channel, where I try get current value from PIT_1 Timer[0]. This is setup as FreeRunning.
Seems that SIUL2 is set correctly for PTDA and I can see toggling on this pin when signal (1Hz) from signal generator is connect on related MCU pin.

But DMA not working for me
My guess here is that I have problem with finding proper chain from PTD6 ->DMAMUX-> DMA channel 4. and find where exactly I can find these information.

From S32K3xx_DMAMUX_map.xlsx I got this:

so here is my first issue: Which source->request is dedicated for PTD6(EIRQ14) ?
And how is related Table 44 from RM manual?

Here is fragments of my code which I working on now:
Setup PTD6

void Setup_PTD6_EIRQ14_for_DMA(void)

{

/* 1. Configuration of physical pin PTD6 via MSCR register */

// PTD6 corresponds to index MSCR[102] (as seen on your screenshot)

IP_SIUL2->MSCR[102] = 0; // Clear register

IP_SIUL2->MSCR[102] |= (1 << 19); // IBE = 1 (Input Buffer Enable - configures pin as input)

IP_SIUL2->IMCR[542-(512)] = 3u;

// Optional: if the signal floats, you can enable Pull-Up (PUE=1, PUS=1) or Pull-Down (PUE=1, PUS=0)

/* 2. Activation of edge detection on line EIRQ[14] */

// We want to capture the timestamp on every rising edge

IP_SIUL2->IREER0 |= (1 << 14); // IREER0[EIRE14] = 1 (Enable Rising Edge)

IP_SIUL2->IFEER0 &= ~(1 << 14); // IFEER0[EIRE14] = 0 (Disable Falling Edge)

/* 3. Request routing: Change from Interrupt to DMA */

// This step ensures that the edge does not wake up the CPU (NVIC), but triggers the DMA line instead

IP_SIUL2->DIRSR0 |= (1 << 14); // DIRSR0[DIRS14] = 1 (Select DMA Request instead of Interrupt)

/* 4. Final enable of DMA request generation for EIRQ[14] */

IP_SIUL2->DIRER0 |= (1 << 14); // DIRER0[EIRE14] = 1 (Activate DMA request line)

}

and setup DMA channel:

void Setup_eDMA_Channel4_Capture_PIT1(void)

{

/* 1. DMAMUX Initialization for eDMA Channel 4 */

// Map EIRQ14 (source 14) to eDMA channel 4

IP_DMAMUX_1->CHCFG[4] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(7u); // EIRQ14 is source 7 for DMAMUX_1

//IP_DMAMUX_0->CHCFG[4] = 0U;

/* 2. TCD Configuration for Channel 4 pointing to PIT_1 (Exact S32K3 bare-metal syntax) */

// Source: Current value of PIT_1 Timer 0

IP_TCD->TCD4_SADDR = (uint32_t)&(IP_PIT_1->TIMER[0].CVAL);

IP_TCD->TCD4_SOFF = 0; // Source does not increment

IP_TCD->TCD4_ATTR = 0x0202; // 32-bit source, 32-bit destination

// Minor Loop: Number of bytes transferred per single trigger

// In S32K3 this corresponds to the NBYTES_MLOFFNO register (no minor loop linking)

IP_TCD->NBYTES4.TCD4_NBYTES_MLOFFNO = 4; // Transfer 4 bytes (32-bit) per trigger

// Destination: Our array in RAM

IP_TCD->TCD4_DADDR = (uint32_t)dma_timestamps;

IP_TCD->TCD4_DOFF = 4; // Shift by 4 bytes in RAM after each edge

// Circular buffer: wrap around to the beginning after filling the entire array

IP_TCD->TCD4_DLAST_SGA = -(BUFFER_SIZE * 4);

// Major Loop Counter: Total number of iterations in the loop

//IP_TCD->CITTER4.TCD4_CITER_ELINKNO = BUFFER_SIZE;

IP_TCD->CITER4.TCD4_CITER_ELINKNO = BUFFER_SIZE;

IP_TCD->BITER4.TCD4_BITER_ELINKNO = BUFFER_SIZE;

/* 3. eDMA channel activation for hardware triggers via official macro */

//IP_TCD->CH4_CSR |= DMA_TCD_CH4_CSR_ERQ_MASK;

/* 3. eDMA channel activation for hardware triggers (With asynchronous mode enabled) */

// Bit 0 (ERQ) = 1 -> Enables hardware triggers

// Bit 2 (EARQ) = 1 -> Enables asynchronous requests from external pins (SIUL2 EIRQ)

IP_TCD->CH4_CSR |= 3u; // ERQ=1, EARQ=1

}

Here I guess is key line:

IP_DMAMUX_1->CHCFG[4] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(7u); // EIRQ14 is source 7 for DMAMUX_1

where I'm little bit confused which IP_DMAMUX and which DMAMUX_CHCFG_SOURCE I need to use and where is proper information about this.

Best regards
Ondrej

Re: S32K348-GPIO EIRQ to DMA request

Hi@OndrejK

"Is this meaning, that MCU have 32 TCD channels and TCD 0 to 15 is valid for DMAMUX_0 and TCD 15 to31 is for DMAMUX_1 ?"

yes, you can find these info in the datasheet, I copy it for your reference.

Re: S32K348-GPIO EIRQ to DMA request

Hi Senlent,

thank you for your answer.

please, can you pointed me from where popup your meaning about TCD mapping?

Is this meaning, that MCU have 32 TCD channels and TCD 0 to 15 is valid for DMAMUX_0 and TCD 15 to31 is
for DMAMUX_1 ?
So I'm still little bit confused about information regarding DMAMUX and eDMA.

Best regards
Ondrej

Re: S32K348-GPIO EIRQ to DMA request

Hi@OndrejK

Your understanding is correct:

PTD6->EIRQ14->DMAMUX1.SOURCE 7.

IP_DMAMUX_1->CHCFG[4] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(7u);  // EIRQ14 is source 7 for DMAMUX_1

However, the TDC settings are incorrect.

My understanding is that they should be as follows:

IP_DMAMUX_1->CHCFG[0] ->TCD 16

IP_DMAMUX_1->CHCFG[4] -> TCD 20 instead of TCD4