Some customer wants to know how to enable the SOD for MIMX9596DVZXQAC, commercial qualification in 19mm. They want to test the SOD mode which is A55 running at 2.0GHz, there is no any documentation in our NXP side explaining how to do that. Here this article give the describe and enable the Super Overdrive mode on the i.MX95.
1\Introduction the i.MX95 Voltage Operating Modes
The i.MX power architecture is designed with the expectation that a dedicated PMIC supplies all required power rails, ensuring compliance with stringent power-up and power-down sequencing requirements.
Majority of the digital logic is supplied with two supplies: VDD_ARM and VDD_SOC.
VDD_ARM is for the CORTEXAMIX.
VDD_SOC is for the rest of the modules in SoC.
The VDD_SOC has following modes:
Overdrive mode
Nominal mode
Underdrive mode
Suspend mode
The VDD_ARM has following modes:
Super Overdrive mode
Overdrive mode
Nominal mode
Underdrive mode
Suspend mode
The i.MX95 power management architecture is based on multiple performance setpoints controlled by the System Manager (SM). These setpoints control:
- Cortex-A55 operating frequency
- VDD_ARM voltage
- Power consumption
- Thermal dissipation
The available performance modes are:PRK,LOW,NOM,ODV,SOD
Where SOD (Super Overdrive) is available only on qualified 2.0 GHz capable devices such as MIMX9596DVZXQAC.
In our datasheet we can see that for the part number only MIMX9596DVZXQAC A core support the 2.0 GHz.
Details in the naming rules:
For the operating ranges in our datasheet can see the details:
Only the Cortex-A55 support the super overdrive mode, and for the typical voltage is 1.0V. In our reference design the VDD_ARM and VDD_SOC from different PMIC.
And for the frequency of modules can also see in the datasheet, for the default setting is 1.8GHz, the maximum is 2004MHz.
2\ Enable Super Overdrive (SOD) Mode (2.0 GHz) on MIMX9596DVZXQAC
Understanding about SOD mode:
The default NXP BSP SM (System Manager) code will automatically detect if the iMX 95 device it is running on is a 2.0 GHz capable device, and then the code will enable operation at 2.0 GHz with Super Overdrive voltage mode. Linux on the iMX 95 only needs to request 2.0 GHz from the System Manager to enable it.
Default BSP support code:
In the download source code path :
/imx95BSP/tmp/work/imx95_19x19_lpddr5_evk-poky-linux/imx-system-manager/2025q4/git/devices/MIMX95/sm/dev_sm_perf.c
Or in our github source can see the code:
imx-sm/devices/MIMX95/sm/dev_sm_perf.c at master · nxp-imx/imx-sm · GitHub
The NXP BSP already contains logic to detect whether the device supports 2.0 GHz operation
/* Check for 2+GHz device */
if (speedGrade >= 2000000000U)
{
/* 2+GHz devices support PRK, LOW, NOM, ODV, SOD setpoints */
s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM;
}
When the System Manager reads:
speedGrade >= 2000000000
the BSP automatically:
- Enables the SOD performance level
- Enables 2.0 GHz OPP
- Manages required ARM voltage transitions
The above code will enable the SOD without changing anything. Then in Linux you can use performance to run at 2.0GHz.
Using the following command:
echo performance > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor
Then we can check the frequency and voltage of the VDD_ARM.
3\ Enabling SOD on a Non-2.0 GHz EVK (Evaluation Only)
For evaluation on the EVK with the 1.8 GHz i.MX95, the process to enable 2.0 GHz and Super Overdrive voltage mode is to modify a single line of SM (System Manager) code so that 2 GHz is enabled even if the iMX 95 does not report 2 GHz operation is possible.
Change this file:
/MIMX95/sm/dev_sm_perf.c
else
{
/* All other devices support PRK, LOW, NOM, ODV setpoints */
s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 1U;
}// This the the default running code for the 1.8GHz for the i.MX95
FROM: s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 1U;
TO: s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM;//Force to work on the SOD mode.
Then rebuild the imx-system-manager and generate a new image.
Write the images to the i.MX95 19x19 lpddr5 EVK board. Run the board and boot up.
root@imx95-19x19-lpddr5-evk:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
500000 900000 1404000 1800000 2004000
root@imx95-19x19-lpddr5-evk:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
2004000
BCU tool show that VDD_ARM is 1.0v when "running" at 2.0GHz and VDD_ARM is 0.9v when running at 1.8GHz, so the SOD is working.
I did the the above change and tested on NXP imx95 1.8GHz 19x19 lpddr5 EVK board and the SOD worked
4\Summary
So For the MIMX9596DVZXQAC the BSP is expected to automatically detect 2.0 GHz capability and enable SOD mode without source code modifications.
EVK Modification
The forced SM modification described above:
DEV_SM_NUM_PERF_LVL_ARM
is intended only for evaluation and debug purposes. It bypasses the normal speed-grade detection mechanism and should not be considered a production configuration for non-qualified devices.
For the customer's MIMX9596DVZXQAC device:
- No BSP modification should be required.
- System Manager automatically checks the speed grade.
- If the device reports 2.0 GHz capability, SOD is enabled automatically.
- Linux only needs to request the highest CPU frequency.
- SOD operation can be verified by:
Availability of 2004000 kHz
CPU running at 2.0 GHz
VDD_ARM increasing from ~0.9 V to ~1.0 V
This confirms successful operation in Super Overdrive (SOD) Mode.